Constrained piecewise polinomial approximation for hardware implementation of elementary functions.
Antonio G. M. StrolloDavide De CaroNicola PetraEttore NapoliValeria GarofaloPublished in: ICECS (2008)
Keyphrases
- hardware implementation
- elementary functions
- efficient implementation
- signal processing
- fpga implementation
- software implementation
- dedicated hardware
- image processing algorithms
- hardware design
- field programmable gate array
- parallel architecture
- general purpose
- morphological operators
- hardware architecture
- gabor filters
- neural network
- memory management
- data processing
- fpga technology
- pattern recognition