Antonio G. M. Strollo

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 29

Top Topics

Adaptive Filter

Top Venues

Publications

Ettore Napoli, Antonio G. M. Strollo, Efstratios Zacharelos, Gennaro Di Meo
Comprehensive Analysis of Input Order Invariant Approximate 4-2 Compressors for Binary Multipliers. ISCAS (2024)
Luca Tegazzini, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo
Design of a Hardware-Efficient Floating-Point Multiplier with Dynamic Segmentation. PRIME (2024)
Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli
Approximate squaring circuits exploiting recursive architectures. Integr. 91 (2023)
Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli
Approximate Recursive Multipliers Using Low Power Building Blocks. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli
Approximate Recursive Multipliers Using Low Power Building Blocks. ARITH (2022)
Gennaro Di Meo, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section. PRIME (2022)
Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding. ICECS (2020)
Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. ISCAS (2020)
Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra, Gennaro Di Meo
Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor. ISCAS (2020)
Darjn Esposito, Davide De Caro, Gennaro Di Meo, Ettore Napoli, Antonio G. M. Strollo
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. Circuits Syst. Signal Process. 38 (12) (2019)
Gerardo Castellano, Davide De Caro, Darjn Esposito, Paolo Bifulco, Ettore Napoli, Nicola Petra, Emilio Andreozzi, Mario Cesarelli, Antonio G. M. Strollo
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. Circuits Syst. Signal Process. 38 (7) (2019)
Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Variable-Rounded LMS Filter for Low-Power Applications. ApplePies (2019)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Stall-Aware Fixed-Point Implementation of LMS Filters. PRIME (2018)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo
On the Use of Approximate Multipliers in LMS Adaptive Filters. ISCAS (2018)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
Quality-Scalable Approximate LMS Filter. ICECS (2018)
Antonio G. M. Strollo, Darjn Esposito
Approximate computing in the nanoscale era. ICICDT (2018)
Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
Design of Low-Power Approximate LMS Filters with Precision-Scalability. ApplePies (2018)
Davide De Caro, Fabio Tessitore, Gianfranco Vai, Gerardo Castellano, Ettore Napoli, Nicola Petra, Claudio Parrella, Antonio G. M. Strollo
Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines. Circuits Syst. Signal Process. 36 (4) (2017)
Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio G. M. Strollo
A SISO Register Circuit Tailored for Input Data with Low Transition Probability. IEEE Trans. Computers 66 (1) (2017)
Darjn Esposito, Antonio G. M. Strollo, Massimo Alioto
Power-precision scalable latch memories. ISCAS (2017)
Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
On the use of approximate adders in carry-save multiplier-accumulators. ISCAS (2017)
Davide De Caro, Ettore Napoli, Darjn Esposito, Gerardo Castellano, Nicola Petra, Antonio G. M. Strollo
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Ettore Napoli, Gerardo Castellano, Darjn Esposito, Antonio G. M. Strollo
Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence. LASCAS (2016)
Darjn Esposito, Gerardo Castellano, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. ISCAS (2016)
Gerardo Castellano, Davide De Caro, Antonio G. M. Strollo, Danilo Manstretta
A low power control system for real-time tuning of a hybrid transformer-based receiver. ICECS (2016)
Mariangela Genovese, Paolo Bifulco, Davide De Caro, Ettore Napoli, Nicola Petra, Maria Romano, Mario Cesarelli, Antonio G. M. Strollo
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. Integr. 49 (2015)
Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo
FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage. LASCAS (2015)
Giorgio Lopez, Ettore Napoli, Domenico Meglio, Antonio G. M. Strollo
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. ISCAS (2015)
Davide De Caro, Fabio Tessitore, Gianfranco Vai, Nicola Imperato, Nicola Petra, Ettore Napoli, Claudio Parrella, Antonio G. M. Strollo
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. IEEE J. Solid State Circuits 50 (9) (2015)
Davide De Caro, Mariangela Genovese, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
Accurate Fixed-Point Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo
Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering. ApplePies (2014)
Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. Integr. 47 (2) (2014)
Davide De Caro, Michele De Martino, Nicola Petra, Antonio G. M. Strollo
Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint. ApplePies (2014)
Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
Truncated squarer with minimum mean-square error. Microelectron. J. 45 (6) (2014)
Ettore Napoli, Mauro D'Arco, Pasquale Di Cosmo, Mariangela Genovese, Antonio G. M. Strollo
FPGA based system for the generation of noise with programmable power spectrum. ISCAS (2014)
Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo
A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction. SITIS (2014)
Ashkan Ashrafi, Antonio G. M. Strollo, Oscar Gustafsson
Hardware Implementation of Digital Signal Processing Algorithms. J. Electr. Comput. Eng. 2013 (2013)
Nicola Petra, Sebastiano Russo, Davide De Caro, Ettore Napoli, Giancarlo Barbarino, Antonio G. M. Strollo
NORA based TDC in 90 nm CMOS. Microelectron. J. 44 (6) (2013)
Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video. J. Electr. Comput. Eng. 2013 (2013)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
Efficient Logarithmic Converters for Digital Signal Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs (10) (2011)
Antonio G. M. Strollo, Davide De Caro, Nicola Petra
Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations. IEEE Trans. Computers 60 (3) (2011)
Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
Design of Fixed-Width Multipliers With Linear Compensation Function. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2011)
Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Valeria Garofalo, Ettore Napoli, Marino Coppola, Pietro Todisco
Fixed-width CSD multipliers with minimum mean square error. ISCAS (2010)
Davide De Caro, Marino Coppola, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo, Valeria Garofalo
High-speed differential resistor ladder for A/D converters. ISCAS (2010)
Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2010)
Valeria Garofalo, Marino Coppola, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
A novel truncated squarer with linear compensation function. ISCAS (2010)
Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio G. M. Strollo, Claudio Parrella
A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. IEEE J. Solid State Circuits 45 (5) (2010)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
High-Performance Special Function Unit for Programmable 3-D Graphics Processors. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
A high performance floating-point special function unit using constrained piecewise quadratic approximation. ISCAS (2008)
Valeria Garofalo, Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
Low error truncated multipliers for DSP applications. ICECS (2008)
Antonio G. M. Strollo, Davide De Caro, Nicola Petra, Ettore Napoli, Valeria Garofalo
Constrained piecewise polinomial approximation for hardware implementation of elementary functions. ICECS (2008)
Andrea Bonfanti, Davide De Caro, Alfio Dario Grasso, Salvatore Pennisi, Carlo Samori, Antonio G. M. Strollo
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS. IEEE J. Solid State Circuits 43 (6) (2008)
Paolo Pulici, Antonio Girardi, Gian Pietro Vanalli, Roberto Izzi, Giacomo Bernardi, Giancarlo Ripamonti, Antonio G. M. Strollo, Giovanni Campardo
A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2008)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2008)
Nicola Petra, Davide De Caro, Antonio G. M. Strollo
) Multipliers. ECCTD (2007)
Nicola Petra, Davide De Caro, Antonio G. M. Strollo
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme. IEEE Trans. Computers 56 (11) (2007)
Nicola Petra, Davide De Caro, Antonio G. M. Strollo
Design of fixed-width multipliers with minimum mean square error. ECCTD (2007)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS. ISSCC (2006)
Davide De Caro, Nicola Petra, Antonio G. M. Strollo
A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS. ISSCC (2006)
Davide De Caro, Antonio G. M. Strollo
High-performance direct digital frequency synthesizers using piecewise-polynomial approximation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2005)
Antonio G. M. Strollo, Nicola Petra, Davide De Caro
Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers. IEEE Trans. Circuits Syst. II Express Briefs (8) (2005)
Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
A high-speed sense-amplifier based flip-flop. ECCTD (2005)
Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
High-speed direct digital frequency synthesizers in 0.25-μm CMOS. CICC (2004)
Davide De Caro, Ettore Napoli, Antonio G. M. Strollo
Direct digital frequency synthesizers with polynomial hyperfolding technique. IEEE Trans. Circuits Syst. II Express Briefs (7) (2004)
Antonio G. M. Strollo, Davide De Caro
Booth folding encoding for high performance squarer circuits. IEEE Trans. Circuits Syst. II Express Briefs 50 (5) (2003)
Antonio G. M. Strollo, Davide De Caro
Direct digital frequency synthesizers exploiting piecewise linear Chebyshev approximation. Microelectron. J. 34 (11) (2003)
Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. FPL (2003)
Davide De Caro, Ettore Napoli, Antonio G. M. Strollo
ROM-less direct digital frequency synthesizers exploiting polynomial approximation. ICECS (2002)
Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. FPL (2002)
Giacinto Paolo Saggese, Antonio G. M. Strollo, Nicola Mazzocca, Davide De Caro
Shuffled serial adder: an area-latency effective serial adder. ICECS (2002)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese
A reconfigurable 2D convolver for real-time SAR imaging. ICECS (2001)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro
New design of squarer circuits using Booth encoding and folding techniques. ICECS (2001)
Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo
Test pattern generator for hybrid testing of combinational circuits. ICECS (2001)
Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino
Analysis of power dissipation in double edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 8 (5) (2000)
Antonio G. M. Strollo, Ettore Napoli, Davide De Caro
New clock-gating techniques for low-power flip-flops. ISLPED (2000)
Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing. ICECS (1999)
Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli
Power dissipation in one-latch and two-latch double edge triggered flip-flops. ICECS (1999)