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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.
Andrea Bonfanti
Davide De Caro
Alfio Dario Grasso
Salvatore Pennisi
Carlo Samori
Antonio G. M. Strollo
Published in:
IEEE J. Solid State Circuits (2008)
Keyphrases
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high speed
clock frequency
power consumption
cmos technology
low power
hd video
nm technology
low cost
video streaming
real time
image sensor
focal plane
low voltage
dielectric constant
massively parallel
power supply
high bandwidth
high definition
parallel processing
multispectral
high frequency