Edoardo Fusella

Publication Activity (10 Years)

Years Active: 2013-2019
Publications (10 Years): 14

Top Topics

Design Automation

Optical Networks

Power Consumption

Top Venues

ACM Trans. Embed. Comput. Syst.

ACM J. Emerg. Technol. Comput. Syst.

IEEE Trans. Parallel Distributed Syst.

Publications

Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. ACM J. Emerg. Technol. Comput. Syst. 15 (1) (2019)
Mirko Gagliardi, Edoardo Fusella, Alessandro Cilardo
Improving Deep Learning with a customizable GPU-like FPGA-based accelerator. PRIME (2018)
José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61 (2018)
Edoardo Fusella, Alessandro Cilardo
Understanding turn models for adaptive routing: The modular approach. DATE (2018)
Edoardo Fusella, Alessandro Cilardo
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
Edoardo Fusella, Alessandro Cilardo
Lattice-Based Turn Model for Adaptive Routing. IEEE Trans. Parallel Distributed Syst. 29 (5) (2018)
Edoardo Fusella, Jose Flich, Alessandro Cilardo
Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. IEEE Trans. Parallel Distributed Syst. 28 (5) (2017)
Edoardo Fusella, Alessandro Cilardo
ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Edoardo Fusella
A Deterministic Approach to Improve Inter-Domain Parallelism of Clustered MPSoC Interconnects. AINA Workshops (2017)
José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO (2017)
Alessandro Cilardo, Edoardo Fusella
Design automation for application-specific on-chip interconnects: A survey. Integr. 52 (2016)
Edoardo Fusella, Alessandro Cilardo
Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip. ACM Trans. Embed. Comput. Syst. 16 (1) (2016)
Edoardo Fusella, Alessandro Cilardo
PhoNoCMap: An application mapping tool for photonic networks-on-chip. DATE (2016)
Edoardo Fusella, Alessandro Cilardo
Minimizing power loss in optical networks-on-chip through application-specific mapping. Microprocess. Microsystems 43 (2016)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects. ACM Trans. Embed. Comput. Syst. 14 (3) (2015)
Edoardo Fusella, Alessandro Cilardo
Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip. HPCC/CSS/ICESS (2015)
Edoardo Fusella, Jose Flich, Alessandro Cilardo, Antonino Mazzeo
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. SiPhotonics@HiPEAC (2015)
Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. FPL (2015)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca
Automated design space exploration for FPGA-based heterogeneous interconnects. Des. Autom. Embed. Syst. 18 (3-4) (2014)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. DATE (2014)
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Automated synthesis of FPGA-based heterogeneous interconnect topologies. FPL (2013)