David B. Thomas

ORCID

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 33

Top Venues

Imperial College London, UK (PHD)

Education History

Imperial College London, UK

PHD

Publications

Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark L. Vousden, David B. Thomas, Alex Yakovlev, Andrew D. Brown
An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster. IEEE ACM Trans. Comput. Biol. Bioinform. 21 (1) (2024)
Mark Vousden, Jordan Morris, Graeme McLachlan Bragg, Jonathan Beaumont, Ashur Rafiev, Wayne Luk, David B. Thomas, Andrew D. Brown
Event-based high throughput computing: A series of case studies on a massively parallel softcore machine. IET Comput. Digit. Tech. 17 (1) (2023)
Mahyar Shahsavari, David B. Thomas, Marcel van Gerven, Andrew D. Brown, Wayne Luk
Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems. Array 20 (2023)
Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10 (2) (2023)
Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark Vousden, David B. Thomas, Alex Yakovlev, Andrew Brown
An Event-Driven Approach To Genotype Imputation On A Custom RISC-V FPGA Cluster. CoRR (2023)
Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. 16 (2-3) (2022)
Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev
Non-deterministic event brokered computing. HEART (2022)
Mahyar Shahsavari, David B. Thomas, Andrew Brown, Wayne Luk
Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture. ICONS (2021)
Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
General hardware multicasting for fine-grained message-passing architectures. PDP (2021)
Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
Termination detection for fine-grained message-passing architectures. ASAP (2020)
Alexander Rast, Mahyar Shahsavari, Graeme M. Bragg, Mark Vousden, David B. Thomas, Andrew Brown
A Hardware/Application Overlay Model for Large-Scale Neuromorphic Simulation. IJCNN (2020)
Tim Todman, David B. Thomas, Wayne Luk
Exploring performance enhancement of event-driven processor networks. FPT (2020)
Matthew Naylor, Simon W. Moore, David B. Thomas
Tinsel: A Manythread Overlay for FPGA Clusters. FPL (2019)
David B. Thomas
Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools. ARITH (2019)
Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL (2019)
Andrew Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov
POETS: Distributed Event-Based Computing - Scaling Behaviour. PARCO (2019)
David B. Thomas
Templatised Soft Floating-Point for High-Level Synthesis. FCCM (2019)
Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT (2018)
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC (2018)
Shane T. Fleming, David B. Thomas
Injecting FPGA Configuration Faults in Parallel. FPT (2018)
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR (2018)
Aryan Tavakkoli, David B. Thomas
A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC (2018)
Shane T. Fleming, David B. Thomas
Using Runahead Execution to Hide Memory Latency in High Level Synthesis. FCCM (2017)
Gordon Inggs, David B. Thomas, Wayne Luk
A Domain Specific Approach to High Performance Heterogeneous Computing. IEEE Trans. Parallel Distributed Syst. 28 (1) (2017)
Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew Brown
Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops (2017)
Andrew Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski
Distributed Event-Based Computing. PARCO (2017)
Jiang Su, David B. Thomas, Peter Y. K. Cheung
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM (2016)
Shane T. Fleming, David B. Thomas
StitchUp: automatic control flow protection for high level synthesis circuits. DAC (2016)
Zeping Xue, David B. Thomas
SynADT: Dynamic Data Structures in High Level Synthesis. FCCM (2016)
Peter Ogden, David B. Thomas, Peter R. Pietzuch
AT-GIS: Highly Parallel Spatial Query Processing with Associative Transducers. SIGMOD Conference (2016)
David B. Thomas
Synthesisable recursion for C++ HLS tools. ASAP (2016)
Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News 44 (4) (2016)
Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica
PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL (2015)
Gordon Inggs, David B. Thomas, Wayne Luk
An Efficient, Automatic Approach to High Performance Heterogeneous Computing. CoRR (2015)
Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk
Pipelined Genetic Propagation. FCCM (2015)
Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston
Recursive pipelined genetic propagation for bilevel optimisation. FPL (2015)
Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA (2015)
Gordon Inggs, David B. Thomas, George A. Constantinides, Wayne Luk
Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR (2015)
David B. Thomas
A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs. ARITH (2015)
David B. Thomas
The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator. ACM Trans. Reconfigurable Technol. Syst. 8 (4) (2015)
Zeping Xue, David B. Thomas
SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems. FPL (2015)
Takaaki Miyajima, David B. Thomas, Hideharu Amano
A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms. J. Inf. Process. 23 (2) (2015)
David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica
Transparent linking of compiled software and synthesized hardware. DATE (2015)
Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk
Parallel Genetic Algorithms on Multiple FPGAs. SIGARCH Comput. Archit. News 43 (4) (2015)
Liucheng Guo, Andreea-Ingrid Funie, Zhongliu Xie, David B. Thomas, Wayne Luk
A general-purpose framework for FPGA-accelerated genetic algorithms. Int. J. Bio Inspired Comput. 7 (6) (2015)
Takaaki Miyajima, David B. Thomas, Hideharu Amano
Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Aryan Tavakkoli, David B. Thomas
Low-latency option pricing using systolic binomial trees. FPT (2014)
Gordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk
Is high level synthesis ready for business? A computational finance case study. FPT (2014)
Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk
Automated framework for FPGA-based parallel genetic algorithms. FPL (2014)
Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides
Compiling Higher Order Functional Programs to Composable Digital Hardware. FCCM (2014)
David B. Thomas
FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy. FCCM (2014)
Gordon Inggs, David B. Thomas, Wayne Luk
A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility. CoRR (2014)
Liucheng Guo, David B. Thomas, Wayne Luk
Automated Framework for General-Purpose Genetic Algorithms in FPGAs. EvoApplications (2014)
Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides
Area implications of memory partitioning for high-level synthesis on FPGAs. FPL (2014)
Takaaki Miyajima, David B. Thomas, Hideharu Amano
An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms. CoRR (2014)
Shane T. Fleming, David B. Thomas
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. FPL (2014)
David B. Thomas, Hideharu Amano
A fully pipelined FPGA architecture for stochastic simulation of chemical systems. FPL (2013)
David B. Thomas, Wayne Luk
Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Shane T. Fleming, David B. Thomas
FPGA based control for real time systems. FPL (2013)
Gordon Inggs, David B. Thomas, Wayne Luk
A Heterogeneous Computing Framework for Computational Finance. ICPP (2013)
Peter Ogden, David B. Thomas, Peter R. Pietzuch
Scalable XML Query Processing using Parallel Pushdown Transducers. Proc. VLDB Endow. 6 (14) (2013)
Liucheng Guo, David B. Thomas, Wayne Luk
Customisable architectures for the set covering problem. SIGARCH Comput. Archit. News 41 (5) (2013)
David B. Thomas, Wayne Luk
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Shane T. Fleming, David B. Thomas
Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields. ARC (2013)
David B. Thomas
Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform. FCCM (2013)
Anson H. T. Tse, David B. Thomas, Wayne Luk
Design Exploration of Quadrature Methods in Option Pricing. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk
Optimising Performance of Quadrature Methods with Reduced Precision. ARC (2012)
Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. FPL (2012)
Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas
A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. FPGA (2012)
Takaaki Miyajima, David B. Thomas, Hideharu Amano
A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU. ICNC (2012)
Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. ASAP (2012)
Qiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas
Optimising explicit finite difference option pricing for dynamic constant reconfiguration. FPL (2012)
Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston
Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. ARC (2012)
Gordon Inggs, David B. Thomas, Simon Winberg
Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA. FPL (2012)
Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj
A framework for FPGA acceleration of large graph problems: Graphlet counting case study. FPT (2011)
Qiwei Jin, Wayne Luk, David B. Thomas
On Comparing Financial Option Price Solvers on FPGA. FCCM (2011)
Qiwei Jin, Wayne Luk, David B. Thomas
Unifying Finite Difference Option-Pricing for Hardware Acceleration. FPL (2011)
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
Efficient reconfigurable design for pricing asian options. SIGARCH Comput. Archit. News 38 (4) (2010)
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. FPT (2010)
David B. Thomas, Wayne Luk
An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. ASAP (2010)
Brahim Betkaoui, David B. Thomas, Wayne Luk
Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT (2010)
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. FPL (2010)
David B. Thomas, Wayne Luk
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. FPL (2010)
Anson H. T. Tse, David B. Thomas, Wayne Luk
Accelerating Quadrature Methods for Option Valuation. FCCM (2009)
David B. Thomas, Lee W. Howes, Wayne Luk
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. FPGA (2009)
Gareth W. Morris, David B. Thomas, Wayne Luk
FPGA Accelerated Low-Latency Market Data Feed Processing. Hot Interconnects (2009)
Qiwei Jin, David B. Thomas, Wayne Luk
Exploring reconfigurable architectures for explicit finite difference option pricing models. FPL (2009)
David B. Thomas, Wayne Luk
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. FCCM (2009)
Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. ACM Trans. Reconfigurable Technol. Syst. 2 (4) (2009)
Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC (2008)
David B. Thomas, Wayne Luk
Estimation of sample mean and variance for Monte-Carlo simulations. FPT (2008)
David B. Thomas, Wayne Luk
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. 1 (2) (2008)
Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC (2008)
David B. Thomas, Wayne Luk
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. FCCM (2008)
David B. Thomas, Wayne Luk
FPGA-optimised high-quality uniform random number generators. FPGA (2008)
David B. Thomas, Wayne Luk
Resource efficient generators for the floating-point uniform and exponential distributions. ASAP (2008)
David B. Thomas, Wayne Luk
Sampling from the exponential distribution using independent Bernoulli variates. FPL (2008)
David B. Thomas, Wayne Luk
A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. FPT (2007)
David B. Thomas, Wayne Luk, Michael Stumpf
Reconfigurable Hardware Acceleration of Canonical Graph Labelling. ARC (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

David B. Thomas