An FPGA run-time parameterisable Log-Normal Random Number Generator.
Pedro EcheverríaDavid B. ThomasMarisa López-VallejoWayne LukPublished in: ARC (2008)
Keyphrases
- log normal
- random number generator
- random number
- high speed
- field programmable gate array
- hardware implementation
- data sets
- verilog hdl
- shift register
- real time image processing
- information retrieval
- signal processing
- low cost
- systolic array
- real time
- hardware design
- hardware architecture
- dedicated hardware
- data streams
- website
- fingerprint authentication