Marisa López-Vallejo

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 21

Top Topics

Interaction Model

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Víctor Manuel Bautista, Mario Garrido, Marisa López-Vallejo
Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón
Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. DCIS (2023)
Hernan Aparicio, Pablo Ituero, Marisa López-Vallejo
Reference-free power supply monitor with enhanced robustness against process and temperature variations. Integr. 82 (2022)
Samuel López Asunción, Pablo Ituero, Marisa López-Vallejo, Jesús Grajal
Data Synchronization in Non-Uniform Latency Custom DSP Designs. DCIS (2022)
Miguel Molina, Javier Mendez, Diego Pedro Morales, Encarnación Castillo, Marisa López-Vallejo, Manuel Pegalajar
Power-Efficient Implementation of Ternary Neural Networks in Edge Devices. IEEE Internet Things J. 9 (20) (2022)
Amadeo de Gracia Herranz, Marisa López-Vallejo
Time to Digital Sensing for Multilevel RRAM Cells. IEEE Access 9 (2021)
Javier De Mena Pacheco, Marisa López-Vallejo
A 65nm Current and Voltage Reference with Improved Line Regulation for Implantable Biosensors. DCIS (2021)
Asghar Bahramali, Marisa López-Vallejo, Carlos A. López-Barrio
An ultra-low power deep sub-micron fast start-up circuit with added line regulation. DCIS (2020)
Samuel López Asunción, Marisa López-Vallejo, Jesús Grajal
Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms. DCIS (2020)
Amadeo de Gracia Herranz, Marisa López-Vallejo
Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations. Integr. 75 (2020)
Asghar Bahramali, Marisa López-Vallejo
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage. Integr. 67 (2019)
Asghar Bahramali, Marisa López-Vallejo, Carlos A. López-Barrio
A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology. DCIS (2019)
Amadeo de Gracia Herranz, Marisa López-Vallejo
Temperature-aware writing architecture for multilevel memristive cells. PATMOS (2019)
Asghar Bahramali, Marisa López-Vallejo
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications. PATMOS (2018)
Fernando García-Redondo, Marisa López-Vallejo
Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2018)
Daniel Fortun, Carlos Garcia de la Cueva, Jesús Grajal, Marisa López-Vallejo, Carlos A. López-Barrio
Performance-oriented Implementation of Hilbert Filters on FPGAs. DCIS (2018)
Fernando García-Redondo, Marisa López-Vallejo, Carlos A. López-Barrio
Advanced integration of variability and degradation in RRAM SPICE compact models. SMACD (2017)
Fernando García-Redondo, Pablo Royer, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero, Carlos A. López-Barrio
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Fernando García-Redondo, Robert P. Gowers, Albert Crespo-Yepes, Marisa López-Vallejo, Liudi Jiang
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Jose M. Nadal-Serrano, Marisa López-Vallejo
A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model. IEEE Trans. Parallel Distributed Syst. 27 (6) (2016)
Fernando García-Redondo, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero
Reliable design methodology: The combined effect of radiation, variability and temperature. SMACD (2016)
Fernando García-Redondo, Marisa López-Vallejo, Pablo Ituero
A thermal adaptive scheme for reliable write operation on RRAM based architectures. ICCD (2015)
Ignacio Herrera-Alzu, Marisa López-Vallejo, C. Gil Soriano
A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs. DFTS (2015)
Javier Agustin, Marisa López-Vallejo
An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Victor Iglesias, Jesús Grajal, Miguel A. Sánchez Marcos, Marisa López-Vallejo
Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms. IEEE Trans. Instrum. Meas. 64 (2) (2015)
Victor Iglesias, Jesús Grajal, Pablo Royer, Miguel A. Sánchez Marcos, Marisa López-Vallejo, Omar A. Yeste Ojeda
Real-time low-complexity automatic modulation classifier for pulsed radar signals. IEEE Trans. Aerosp. Electron. Syst. 51 (1) (2015)
Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm. NANOARCH (2015)
Carlos Gómez Osuna, Pablo Ituero, Marisa López-Vallejo
A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs). Sensors 14 (1) (2014)
Pablo Ituero, Marisa López-Vallejo, Carlos A. López-Barrio
0.64 nJ Leakage-Based CMOS Temperature Sensor. Sensors 13 (9) (2013)
Pablo Royer, Marisa López-Vallejo
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. ACM Great Lakes Symposium on VLSI (2013)
Carlos Benito, Pablo Ituero, Marisa López-Vallejo
A Low-Area Reference-Free Power Supply Sensor. DSD (2013)
Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, Bogdan Pasca
Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 6 (1) (2013)
Pedro Echeverría, Marisa López-Vallejo
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator. J. Signal Process. Syst. 71 (2) (2013)
Miguel Angel Sánchez, Marisa López-Vallejo, Carlos Angel Iglesias
Hardware Reuse Improvement through the Domain Specific Language dHDL. ISPA (2012)
Miguel Angel Sánchez, Marisa López-Vallejo, Carlos Angel Iglesias, Carlos A. López-Barrio
Improving Hardware Reuse through XML-based Interface Encapsulation. ICECCS (2012)
Carlos Gómez Osuna, Miguel A. Sánchez Marcos, Pablo Ituero, Marisa López-Vallejo
A monitoring infrastructure for FPGA self-awareness and dynamic adaptation. ICECS (2012)
Pedro Echeverría, Marisa López-Vallejo
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. Microprocess. Microsystems 35 (6) (2011)
Pablo Ituero, Marisa López-Vallejo, Miguel A. Sánchez Marcos, Carlos Gómez Osuna
On-chip Monitoring: A Light-Weight Interconnection Network Approach. DSD (2011)
Jesús Grajal, Omar A. Yeste Ojeda, Miguel Angel Sánchez, Mario Garrido, Marisa López-Vallejo
Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications. EUSIPCO (2011)
Ignacio Herrera-Alzu, Marisa López-Vallejo
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. PATMOS (2011)
José Luis Ayala, Cándido Méndez, Marisa López-Vallejo
Thermal analysis and modeling of embedded processors. Comput. Electr. Eng. 36 (1) (2010)
Pedro Echeverría, Marisa López-Vallejo, Walter Bolognesi, Carlos A. López-Barrio
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs. ICECS (2009)
David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. Integr. 41 (1) (2008)
Pedro Echeverría, Marisa López-Vallejo, Jose María Pesquero
Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach. ICECS (2008)
Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC (2008)
Ignacio Herrera-Alzu, Miguel Angel Sánchez, Marisa López-Vallejo, Pedro Echeverría
Experimental methodology for power characterization of FPGAs. ICECS (2008)
Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo
Power Considerations in Banked CAMs: A Leakage Reduction Approach. VLSI Design 2008 (2008)
José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. Int. J. Embed. Syst. 3 (4) (2008)
Angel Fernandez Herrero, Ignacio Elguezábal, Marisa López-Vallejo
A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. e-Learning (2008)
Miguel Angel Sánchez, Pedro Echeverría, Francisco Mansilla, Marisa López-Vallejo
Designing Highly Parameterized Hardware using xHdl. FDL (2008)
Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. ICESS (2007)
Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. ISCAS (2007)
José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest
Energy-aware compilation and hardware design for VLIW embedded systems. Int. J. Embed. Syst. 3 (1/2) (2007)
Pablo Ituero, José L. Ayala, Marisa López-Vallejo
Leakage-based On-Chip Thermal Sensor for CMOS Technology. ISCAS (2007)
José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio
Thermal Characterization and Thermal Management in Processor-Based Systems. Power-aware Computing Systems (2007)
David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
Compiler-Driven Leakage Energy Reduction in Banked Register Files. PATMOS (2006)
Pablo Ituero, Marisa López-Vallejo
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. ASAP (2006)
Cándido Méndez, José Luis Ayala, Marisa López-Vallejo
Target Independent Thermal Modeling for Embedded Processors. IES (2006)
Miguel A. Sánchez Marcos, Mario Garrido, Marisa López-Vallejo, Carlos A. López-Barrio
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation. FPT (2006)
José Luis Ayala, Cándido Méndez, Marisa López-Vallejo
Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors. ICECS (2006)
Pedro Echeverría, José Luis Ayala, Marisa López-Vallejo
Leakage Energy Reduction in Banked Content Addressable Memories. ICECS (2006)
José Luis Ayala, Marisa López-Vallejo
Integrating functional and power simulation in embedded systems design. J. Embed. Comput. 1 (3) (2005)
José Luis Ayala, Marisa López-Vallejo
Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. Power-aware Computing Systems (2005)
Marcos M. A. Sanchez, Fernandez Herrero, Marisa López-Vallejo
Improving IP core reuse through the application of the meta-language xHDL. FDL (2004)
Inkyu Lee, Marisa López-Vallejo, Syed Aon Mujtaba
Block processing technique for low power turbo decoder design. VTC Spring (2002)