Angel Fernandez Herrero

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Motion Estimation Algorithm

Allocation Scheme

Simulation Platform

Top Venues

EURASIP J. Adv. Signal Process.

J. Circuits Syst. Comput.

Publications

Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. J. Circuits Syst. Comput. 21 (7) (2012)
Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. EURASIP J. Adv. Signal Process. 2012 (2012)
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
Fast fixed-point optimization of DSP algorithms. VLSI-SoC (2010)
Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) (2010)
Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO (2010)
Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
Improved schemes for tracking residual frequency offset in DVB-T systems. IEEE Trans. Consumer Electron. 56 (2) (2010)
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010)
Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Francisco Javier Casajús-Quirós
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver. VLSI Design 2008 (2008)
Angel Fernandez Herrero, Ignacio Elguezábal, Marisa López-Vallejo
A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. e-Learning (2008)
Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. FPL (2006)
Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Javier Casajús-Quirós
Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver. ICECS (2006)