Carlos Carreras

Publication Activity (10 Years)

Years Active: 1994-2019
Publications (10 Years): 4

Top Topics

Code Generation

Stream Processing

Rapid Prototyping

Top Venues

Publications

Roberto Sierra, Filippo Mangani, Carlos Carreras, Gabriel Caffarena
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. FPL (2019)
Roberto Sierra, Carlos Carreras, Gabriel Caffarena
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. Integr. 68 (2019)
Roberto Sierra, Carlos Carreras, Gabriel Caffarena
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. PATMOS (2018)
Roberto Sierra, Carlos Carreras, Gabriel Caffarena, Carlos A. López Bario
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (1) (2015)
Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. J. Syst. Archit. 60 (7) (2014)
Bojan Jovanovic, Ruzica Jevtic, Carlos Carreras
Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. IEEE Trans. Ind. Informatics 10 (1) (2014)
Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. J. Circuits Syst. Comput. 21 (7) (2012)
Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. EURASIP J. Adv. Signal Process. 2012 (2012)
Ruzica Jevtic, Carlos Carreras
A complete dynamic power estimation model for data-paths in FPGA DSP designs. Integr. 45 (2) (2012)
Pablo Barrio, Carlos Carreras, Roberto Sierra, Tobias Kenter, Christian Plessl
Turning control flow graphs into function calls: Code generation for heterogeneous architectures. HPCS (2012)
Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras
Power estimation of dividers implemented in FPGAs. ACM Great Lakes Symposium on VLSI (2011)
Pablo Barrio, Carlos Carreras
Mesh traversal and sorting for efficient memory usage in scientific codes. IPCCC (2011)
Ruzica Jevtic, Carlos Carreras
Power Measurement Methodology for FPGA Devices. IEEE Trans. Instrum. Meas. 60 (1) (2011)
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
Fast fixed-point optimization of DSP algorithms. VLSI-SoC (2010)
Gabriel Caffarena, Carlos Carreras
Precision-wise architectural synthesis of DSP circuits. EUSIPCO (2010)
Gabriel Caffarena, Carlos Carreras
Architectural synthesis of DSP circuits under simultaneous error and time constraints. VLSI-SoC (2010)
Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) (2010)
Ruzica Jevtic, Carlos Carreras
Power Estimation of Embedded Multiplier Blocks in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 18 (5) (2010)
Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO (2010)
Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
Improved schemes for tracking residual frequency offset in DVB-T systems. IEEE Trans. Consumer Electron. 56 (2) (2010)
Javier Gonzalez Bayon, Carlos Carreras, Ove Edfors
A Multistandard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE, and DVB-T/H Systems. J. Comput. Networks Commun. 2010 (2010)
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010)
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
Floorplan-based FPGA interconnect power estimation in DSP circuits. SLIP (2009)
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfigurable Comput. 2009 (2009)
Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras, Atta Badii
A Practical Method for Testing High-Speed Networking Hardware Architectures. ICNS (2009)
Slobodan Bojanic, Vukasin Pejovic, Gabriel Caffarena, Vladimir M. Milovanovic, Carlos Carreras, Jelena Popovic
Behavioural Biometrics Hardware Based on Bioinformatics Matching. CISIS (2009)
Ruzica Jevtic, Carlos Carreras
Analytical High-Level Power Model for LUT-Based Components. PATMOS (2008)
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig (2008)
Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits Devices Syst. 2 (4) (2008)
Ruzica Jevtic, Carlos Carreras, Domenik Helms
A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. ReConFig (2008)
Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena
Switching Activity Models for Power Estimation in FPGA Multipliers. ARC (2007)
Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras
A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. ERSA (2007)
Gabriel Caffarena, Carlos E. Pedreira, Carlos Carreras, Slobodan Bojanic, Octavio Nieto-Taladriz
Fpga Acceleration for DNA Sequence Alignment. J. Circuits Syst. Comput. 16 (2) (2007)
Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras
Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware. SECURWARE (2007)
Gabriel Caffarena, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras, Octavio Nieto-Taladriz
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs (5) (2006)
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. SoC (2006)
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL (2006)
Robin McDonnell, George Grimes, Ian D. Walker, Carlos Carreras
Extension versus bending for continuum robots. ICINCO (2005)
Gabriel Caffarena, Angel Fernández, Carlos Carreras, Octavio Nieto-Taladriz
Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach. EUSIPCO (2004)
Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
A Generator of High-Speed Floating-Point Modules. FCCM (2004)
Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
Analysis of limit cycles by means of affine arithmetic computer-aided tests. EUSIPCO (2004)
Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz
Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) (2003)
Carlos Carreras, Ian D. Walker
Interval methods for fault-tree analysis in robotics. IEEE Trans. Reliab. 50 (1) (2001)
Carlos Carreras, Ian D. Walker
On interval methods applied to robot reliability quantification. Reliab. Eng. Syst. Saf. 70 (3) (2000)
Carlos Carreras, Manuel V. Hermenegildo
Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions. SARA (2000)
Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz
Bit-Width Selection for Data-Path Implementations. ISSS (1999)
Carlos Carreras, Juan Carlos López, María Luisa López Vallejo, Luis Sánchez, Carlos Delgado Kloos, Natividad Martínez Madrid
A Co-Design Methodology Based on Formal Specification and High-level Estimation. CODES (1996)
Carlos Carreras, Carlos A. López Bario, Manuel V. Hermenegildo
Analytic Model of a Cache Only Memory Architecture. PARLE (1994)