Floorplan-based FPGA interconnect power estimation in DSP circuits.
Ruzica JevticCarlos CarrerasVukasin PejovicPublished in: SLIP (2009)
Keyphrases
- power dissipation
- digital signal processing
- high speed
- power reduction
- signal processing
- low power
- field programmable gate array
- power consumption
- data flow
- low power consumption
- chip design
- image processing
- logic circuits
- verilog hdl
- cmos technology
- systolic array
- real time
- real time image processing
- hardware implementation
- accurate estimation
- computer vision and image processing
- estimation algorithm
- estimation accuracy
- data acquisition
- digital signal
- power management
- analog circuits
- density estimation
- low cost
- pattern recognition
- hardware description language
- hardware architecture