Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.
Roberto SierraCarlos CarrerasGabriel CaffarenaPublished in: PATMOS (2018)
Keyphrases
- low latency
- error propagation
- low power consumption
- hardware implementation
- real time image processing
- high speed
- bit rate
- real time
- rate distortion
- error concealment
- motion vectors
- video coding
- bitstream
- hardware architecture
- fpga implementation
- macroblock
- field programmable gate array
- signal processing
- computational complexity
- high quality