Gabriel Caffarena

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 9

Top Topics

Electron Microscopy

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Ruzica Jevtic, Pablo Perez-Tirador, Carmen Cabezaolias, Pablo Carnero, Gabriel Caffarena
Side-channel Attack Countermeasure Based on Power Supply Modulation. EUSIPCO (2022)
Abraham Otero, Paulo Félix, David G. Márquez, Constantino A. García, Gabriel Caffarena
A fault-tolerant clustering algorithm for processing data from multiple streams. Inf. Sci. 584 (2022)
Javier Hormigo, Gabriel Caffarena
FPGA acceleration of bit-true simulations for word-length optimization. ARITH (2021)
Roberto Sierra, Filippo Mangani, Carlos Carreras, Gabriel Caffarena
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. FPL (2019)
Roberto Sierra, Carlos Carreras, Gabriel Caffarena
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. Integr. 68 (2019)
Roberto Sierra, Carlos Carreras, Gabriel Caffarena
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. PATMOS (2018)
Gabriel Caffarena, Daniel Ménard
Quantization Noise Power Estimation for Floating-Point DSP Circuits. IEEE Trans. Circuits Syst. II Express Briefs (6) (2016)
Kartik Lakhotia, Gabriel Caffarena, Alberto Gil, David G. Márquez, Abraham Otero, Madhav P. Desai
Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array. IWBBIO (2016)
Pablo Pérez-Tirador, Gabriel Caffarena, Constantino A. García, Abraham Otero, Rafael Raya, Rodrigo García-Carmona
Hardware Accelerator to Compute the Minimum Embedding Dimension of ECG Records. IWBBIO (2016)
Roberto Sierra, Carlos Carreras, Gabriel Caffarena, Carlos A. López Bario
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (1) (2015)
Ana Iriarte, Gabriel Caffarena, Mariano Lopez-Fernandez, Rodrigo García-Carmona, Abraham Otero, Carlos Oscar Sánchez Sorzano, Roberto Marabini
Iterative reconstruction for pet scanners with continuous scintillators. EMBC (2015)
Carlos Oscar Sánchez Sorzano, Javier Vargas, José Miguel de la Rosa-Trevín, Airen Zaldívar-Peraza, Joaquín Otón, Vahid Abrishami, Ignacio Foche, Roberto Marabini, Gabriel Caffarena, José María Carazo
Outlier detection for single particle analysis in Electron Microscopy. IWBBIO (2014)
Eduardo Garcia de La Cueva, Miguel Mateo de La Puente, Alessandro Deideri, Ana Iriarte, Carlos Oscar Sánchez Sorzano, Gabriel Caffarena
2D and 3D Alignment for Electron Microscopy via Graphics Processing Units. IWBBIO (2014)
Alberto Gil, Gabriel Caffarena, David G. Márquez, Abraham Otero
Hermite Polynomial Characterization of Heartbeats with Graphics Processing Units. IWBBIO (2014)
Pablo Calleja, Gabriel Caffarena, Ana Iriarte
FPGA Design of Delay-Based Digital Effects for Electric Guitar. ARC (2014)
Eduardo I. Boemo, Juan P. Oliver, Gabriel Caffarena
Tracking the pipelining-power rule along the FPGA technical literature. FPGAworld (2013)
Javier Hormigo, Gabriel Caffarena, Juan P. Oliver, Eduardo I. Boemo
Self-Reconfigurable Constant Multiplier for FPGA. ACM Trans. Reconfigurable Technol. Syst. 6 (3) (2013)
Gabriel Caffarena, Olivier Sentieys, Daniel Ménard, Juan A. López, David Novo
Quantization of VLSI digital signal processing systems. EURASIP J. Adv. Signal Process. 2012 (2012)
Carlos Oscar Sánchez Sorzano, Joaquín Otón, Jesús Cuenca Alba, Airen Zaldívar-Perez, Gabriel Caffarena, Javier Sanchez-Jimenez, Cédric Messaoudi, Sergio Marco, Roberto Marabini, José María Carazo
Image processing for Cellular tomography using soft X-rays. ISBI (2012)
Jean-Charles Naud, Daniel Ménard, Gabriel Caffarena, Olivier Sentieys
A Discrete Model for Correlation Between Quantization Noises. IEEE Trans. Circuits Syst. II Express Briefs (11) (2012)
Gabriel Caffarena, Daniel Ménard
Many-core parallelization of fixed-point optimization of VLSI circuits through GPU devices. DASIP (2012)
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
Fast fixed-point optimization of DSP algorithms. VLSI-SoC (2010)
Gabriel Caffarena, Carlos Carreras
Precision-wise architectural synthesis of DSP circuits. EUSIPCO (2010)
Gabriel Caffarena, Carlos Carreras
Architectural synthesis of DSP circuits under simultaneous error and time constraints. VLSI-SoC (2010)
Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) (2010)
Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO (2010)
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010)
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfigurable Comput. 2009 (2009)
Slobodan Bojanic, Vukasin Pejovic, Gabriel Caffarena, Vladimir M. Milovanovic, Carlos Carreras, Jelena Popovic
Behavioural Biometrics Hardware Based on Bioinformatics Matching. CISIS (2009)
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig (2008)
Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits Devices Syst. 2 (4) (2008)
Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena
Switching Activity Models for Power Estimation in FPGA Multipliers. ARC (2007)
Gabriel Caffarena, Carlos E. Pedreira, Carlos Carreras, Slobodan Bojanic, Octavio Nieto-Taladriz
Fpga Acceleration for DNA Sequence Alignment. J. Circuits Syst. Comput. 16 (2) (2007)
Gabriel Caffarena, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras, Octavio Nieto-Taladriz
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs (5) (2006)
Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. FPL (2006)
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. SoC (2006)
Slobodan Bojanic, Gabriel Caffarena, Slobodan Petrovic, Octavio Nieto-Taladriz
FPGA for pseudorandom generator cryptanalysis. Microprocess. Microsystems 30 (2) (2006)
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL (2006)
Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz
High-speed systolic array for gene matching. FPGA (2004)
Gabriel Caffarena, Angel Fernández, Carlos Carreras, Octavio Nieto-Taladriz
Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach. EUSIPCO (2004)
Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
A Generator of High-Speed Floating-Point Modules. FCCM (2004)
Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
Analysis of limit cycles by means of affine arithmetic computer-aided tests. EUSIPCO (2004)
Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz
Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) (2003)