Madhav P. Desai

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 8

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Ibm Zenterprise

Memory Subsystem

Top Venues

Publications

Madhav P. Desai
An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache. CoRR (2023)
Neha V. Karanjkar, Madhav P. Desai
Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration. SIMULTECH (2022)
Madhav P. Desai, Aniket Deshmukh
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches. CoRR (2021)
Nanditha P. Rao, Madhav P. Desai
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. Microelectron. J. 72 (2018)
Nanditha P. Rao, Madhav P. Desai
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. CoRR (2017)
Nanditha P. Rao, Madhav P. Desai
Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. CoRR (2016)
Neha V. Karanjkar, Madhav P. Desai
On Continuous-space Embedding of Discrete-parameter Queuing Systems. CoRR (2016)
Kartik Lakhotia, Gabriel Caffarena, Alberto Gil, David G. Márquez, Abraham Otero, Madhav P. Desai
Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array. IWBBIO (2016)
Nanditha P. Rao, Madhav P. Desai
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. DSD (2015)
Neha V. Karanjkar, Madhav P. Desai
An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique. MASCOTS (2015)
Neha V. Karanjkar, Madhav P. Desai
Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique. CoRR (2014)
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
On the likelihood of multiple bit upsets in logic circuits. CoRR (2014)
Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai
The Click2NetFPGA Toolchain. USENIX Annual Technical Conference (2012)
Madhav P. Desai
On Cycles in Random Graphs CoRR (2010)
Gautam Hazari, Madhav P. Desai, G. Srinivas
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. VLSI Design (2010)
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. DSD (2010)
Pratyush Kumar, Madhav P. Desai
Learning based address mapping for improving the performance of memory subsystems. MASCOTS (2009)
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. VLSI Design (2007)
Gaurav Trivedi, Madhav P. Desai, H. Narayanan
Parallelization of DC Analysis through Multiport Decomposition. VLSI Design (2007)
Gautam Hazari, Madhav P. Desai, H. Kasture
On the Impact of Address Space Assignment on Performance in Systems-on-Chip. VLSI Design (2007)
Gaurav Trivedi, Madhav P. Desai, H. Narayanan
Fast DC Analysis and Its Application to Combinatorial Optimization Problems. VLSI Design (2006)
Madhav P. Desai, D. Manjunath
On Range Matrices and Wireless Networks in d Dimensions. WiOpt (2005)
Shabbir H. Batterywala, Madhav P. Desai
Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design (2005)
Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty
A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. VLSI Design (2004)
Vani Prasad, Madhav P. Desai
On Buffering Schemes for Long Multi-Layer Nets. VLSI Design (2004)
Aditya Mittal, Madhav P. Desai
A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. VLSI Design (2004)
Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. VLSI Design (2003)
Madhav P. Desai, H. Narayanan, Sachin B. Patkar
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. Discret. Appl. Math. 131 (2) (2003)
Vani Prasad, Madhav P. Desai
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. VLSI Design (2003)
Maryam Shojaei Baghini, Madhav P. Desai
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. VLSI Design (2002)
Madhav P. Desai, D. Manjunath
On the connectivity in finite ad hoc networks. IEEE Commun. Lett. 6 (10) (2002)
Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao
Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectron. Reliab. 41 (7) (2001)
Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design (2001)
Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai
An On-Chip Coupling Capacitance Measurement Technique. VLSI Design (2001)
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
Inductance Characterization of Small Interconnects Using Test-Signal Method. VLSI Design (2000)
B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai
A State Assignment Scheme Targeting Performance and Area. VLSI Design (1999)
Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
Decomposition of Finite State Machines for Area, Delay Minimization. ICCD (1999)
Nevine Nassif, Madhav P. Desai, Dale H. Hall
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. DAC (1998)
Madhav P. Desai, Yao-Tsung Yen
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. DAC (1996)
Madhav P. Desai, Radenko Cvijetic, James Jensen
Sizing of Clock Distribution Networks for High Performance CPU Chips. DAC (1996)
Madhav P. Desai, Vasant B. Rao
On the Convergence of Reversible Markov Chains. SIAM J. Matrix Anal. Appl. 14 (4) (1993)