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Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.

Nevine NassifMadhav P. DesaiDale H. Hall
Published in: DAC (1998)
Keyphrases
  • high speed
  • circuit design
  • functional verification
  • low cost
  • analog vlsi
  • real time
  • power consumption
  • physical design
  • asynchronous circuits
  • nm technology
  • probabilistic model
  • high frequency
  • focal plane
  • cmos technology