Nevine Nassif

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 3

Top Topics

Multiprocessor Architecture

Memory Efficient

Parallel Processors

Top Venues

IEEE J. Solid State Circuits

Publications

Ashley O. Munch, Nevine Nassif, Carleton L. Molnar, Jason Crop, Rich Gammack, Chinmay P. Joshi, Goran Zelic, Kambiz Munshi, Min Huang, Charles Morganti, Sireesha Kandula, Arijit Biswas
Scalable Processors. ISSCC (2024)
Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor. ISSCC (2022)
William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker
The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family. IEEE J. Solid State Circuits 51 (1) (2016)
William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker
4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family. ISSCC (2015)
Emily J. Shriver, Dale H. Hall, Nevine Nassif, Nadir E. Rahman, Nick L. Rethman, Gill Watt, Jim A. Farrell
Timing verification of the 21264: A 600 MHz full-custom microprocessor. ICCD (1998)
Nevine Nassif, Madhav P. Desai, Dale H. Hall
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. DAC (1998)