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Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology.

Nanditha P. RaoMadhav P. Desai
Published in: Microelectron. J. (2018)
Keyphrases
  • low power
  • logic circuits
  • cmos technology
  • power dissipation
  • power consumption
  • high speed
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  • multi channel
  • low voltage
  • pattern matching
  • computer architecture
  • spl times