Nanditha P. Rao

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 7

Top Topics

Top Venues

Microelectron. J.

Publications

Shubhayu Das, Nanditha P. Rao, Sharad Sinha
ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. IPDPS (Workshops) (2024)
Shivani Shah, Nanditha P. Rao
MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA. ACM Great Lakes Symposium on VLSI (2023)
Shivani Shah, Sahithi Meenakshi Vutakuru, Nanditha P. Rao
FPGA Accelerated Parameterized Cache Simulator. ISQED (2021)
Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao
Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. DSD (2021)
Nanditha P. Rao, Madhav P. Desai
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. Microelectron. J. 72 (2018)
Nanditha P. Rao, Madhav P. Desai
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. CoRR (2017)
Nanditha P. Rao, Madhav P. Desai
Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. CoRR (2016)
Nanditha P. Rao, Madhav P. Desai
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. DSD (2015)
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
On the likelihood of multiple bit upsets in logic circuits. CoRR (2014)