Nihar R. Mohapatra

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 8

Top Topics

Metal Oxide Semiconductor

Analog To Digital Converter

Top Venues

Publications

Rutu Patel, Nihar R. Mohapatra
On the improved RF performance of step field plate LDMOS transistor. Microelectron. J. 148 (2024)
Yadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra
Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications. VDAT (2019)
Tanmay Chavan, Sangya Dutta, Nihar R. Mohapatra, Udayan Ganguly
Band-to-Band Tunneling based Ultra-Energy Efficient Silicon Neuron. CoRR (2019)
Tanmay Chavan, S. Dutta, Nihar R. Mohapatra, Udayan Ganguly
An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology. DRC (2018)
Ashish Soni, Abhijit Umap, Nihar R. Mohapatra
Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs. VDAT (2017)
Apoorva Ojha, Nihar R. Mohapatra
Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model. ESSDERC (2017)
Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma
Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array. ISQED (2016)
Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors. VLSI Design (2016)
Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. VLSI Design (2003)
D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. VLSI Design (2003)
Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao
Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectron. Reliab. 41 (7) (2001)
Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design (2001)