An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology.
Tanmay ChavanS. DuttaNihar R. MohapatraUdayan GangulyPublished in: DRC (2018)
Keyphrases
- energy efficient
- silicon on insulator
- cmos technology
- low power
- wireless sensor networks
- power consumption
- energy efficiency
- high speed
- energy consumption
- sensor networks
- flip flops
- low voltage
- parallel processing
- base station
- power dissipation
- ibm power processor
- routing protocol
- energy saving
- data transmission
- low cost
- routing algorithm
- ad hoc networks
- data center
- smart card