An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache.
Madhav P. DesaiPublished in: CoRR (2023)
Keyphrases
- real time
- low cost
- ibm zenterprise
- multithreading
- memory subsystem
- memory hierarchy
- memory management
- distributed shared memory
- processor core
- embedded processors
- circuit design
- computing power
- computing systems
- control flow
- data flow
- hardware implementation
- hardware and software
- embedded systems
- parallel processing
- data access
- silicon on insulator
- high speed