Shabbir H. Batterywala

Publication Activity (10 Years)

Years Active: 1997-2015
Publications (10 Years): 1

Top Topics

Engineering Design

Top Venues

Publications

Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. VLSI Design (2015)
Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala
Fixing Double Patterning violations with look-ahead. ASP-DAC (2014)
Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
Automatic design rule correction in presence of multiple grids and track patterns. DAC (2013)
Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design (2009)
Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED (2008)
Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED (2008)
Subramanian Rajagopalan, Shabbir H. Batterywala
A 3-dimensional FEM Based Resistance Extraction. VLSI Design (2007)
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design (2007)
Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure
A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. VLSI Design (2006)
Rohit Ananthakrishna, Shabbir H. Batterywala
MoM - A Process Variation Aware Statistical Capacitance Extractor. VLSI Design (2006)
Shabbir H. Batterywala, Madhav P. Desai
Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design (2005)
Shabbir H. Batterywala, Narendra V. Shenoy
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design (2004)
Shabbir H. Batterywala, Narendra V. Shenoy
A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design (2003)
Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD (2002)
Shabbir H. Batterywala, H. Narayanan
Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. VLSI Design (2001)
Shabbir H. Batterywala, H. Narayanan
Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. VLSI Design (1999)
Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan
A New Partitioning Strategy Based on Supermodular Functions. VLSI Design (1997)