Rupesh S. Shelar

Publication Activity (10 Years)

Years Active: 1999-2020
Publications (10 Years): 1

Top Topics

Exhaustive Search

Low Power Consumption

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Rupesh S. Shelar
An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops. FPGA (2020)
Rupesh S. Shelar, Marek Patyra
Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (10) (2013)
Rupesh S. Shelar
A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Yifang Liu, Rupesh S. Shelar, Jiang Hu
Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (3) (2011)
Rupesh S. Shelar
Routing With Constraints for Post-Grid Clock Distribution in Microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Rupesh S. Shelar, Marek Patyra
Impact of local interconnects on timing and power in a high performance microprocessor. ISPD (2010)
Rupesh S. Shelar
An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. ISPD (2009)
Yifang Liu, Rupesh S. Shelar, Jiang Hu
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD (2008)
Rupesh S. Shelar
An efficent clustering algorithm for low power clock tree synthesis. ISPD (2007)
Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD (2005)
Rupesh S. Shelar, Sachin S. Sapatnekar
BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 13 (8) (2005)
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
A predictive distributed congestion metric and its application to technology mapping. ISPD (2004)
Rupesh S. Shelar, Sachin S. Sapatnekar
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. VLSI Design (2002)
Rupesh S. Shelar, Sachin S. Sapatnekar
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS (2002)
Rupesh S. Shelar, Sachin S. Sapatnekar
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD (2001)
Rupesh S. Shelar, Sacheendra Nath, Jagmohan S. Nanaware
Parameterized Reusable Component Library Methodology. EUROMICRO (2000)
Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
Decomposition of Finite State Machines for Area, Delay Minimization. ICCD (1999)