An efficent clustering algorithm for low power clock tree synthesis.
Rupesh S. ShelarPublished in: ISPD (2007)
Keyphrases
- low power
- power consumption
- high speed
- clustering algorithm
- low cost
- single chip
- tree structure
- high power
- vlsi circuits
- low power consumption
- vlsi architecture
- digital signal processing
- logic circuits
- cmos technology
- mixed signal
- power saving
- wireless transmission
- real time
- gate array
- b tree
- index structure
- image processing
- power dissipation
- embedded systems
- power reduction
- computer simulation
- energy dissipation
- signal processing