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Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor.
Rupesh S. Shelar
Marek Patyra
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
Keyphrases
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power consumption
power dissipation
cost effective
functional verification
neural network
high reliability
high speed
low power
design methodology
small sized
power distribution
chip design