Javier Hormigo

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 18

Top Topics

Qr Decomposition

Sparse Matrices

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Computers

Publications

Raul Murillo, Javier Hormigo, Alberto A. Del Barrio, Guillermo Botella
HUB Meets Posit: Arithmetic Units Implementation. IEEE Trans. Circuits Syst. II Express Briefs 71 (1) (2024)
Marco Hormigo-Jiménez, Javier Hormigo
High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS. DCIS (2023)
Julio Villalba, Javier Hormigo
High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst. Signal Process. 41 (3) (2022)
Javier Hormigo, Gabriel Caffarena
FPGA acceleration of bit-true simulations for word-length optimization. ARITH (2021)
Javier Hormigo, Sergio D. Muñoz
Efficient Floating-Point Givens Rotation Unit. Circuits Syst. Signal Process. 40 (5) (2021)
Sonia González-Navarro, Javier Hormigo
New Results on Non-Normalized Floating-Point Formats. IEEE Trans. Computers 69 (12) (2020)
Javier Hormigo, Sergio D. Muñoz
Efficient Floating-Point Givens Rotation Unit. CoRR (2020)
Javier Hormigo, Julio Villalba-Moreno, Sonia Gonzalez-Navarro
Floating-Point Fused Multiply-Add under HUB Format. ARITH (2020)
Javier Hormigo, Andrés Rodríguez
Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden. Rev. Iberoam. de Tecnol. del Aprendiz. 14 (2) (2019)
Julio Villalba, Javier Hormigo, Sonia González-Navarro
Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs (6) (2019)
Julio Villalba-Moreno, Javier Hormigo, Francisco J. Jaime
Reproducible Summation Under HUB Format. ARITH (2019)
Julio Villalba-Moreno, Javier Hormigo, Sonia González-Navarro
Unbiased Rounding for HUB Floating-Point Addition. IEEE Trans. Computers 67 (9) (2018)
Sonia González-Navarro, Javier Hormigo
Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems. ARITH (2017)
Julio Villalba-Moreno, Javier Hormigo
Floating Point Square Root under HUB Format. ICCD (2017)
Javier Hormigo, Jean-Michel Muller, Stuart F. Oberman, Nathalie Revol, Arnaud Tisserand, Julio Villalba-Moreno
Introduction to the Special Issue on Computer Arithmetic. IEEE Trans. Computers 66 (12) (2017)
Javier Hormigo, Julio Villalba
HUB Floating Point for Improving FPGA Implementations of DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs (3) (2017)
Javier Hormigo, Julio Villalba
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Javier Hormigo, Julio Villalba
New Formats for Computing with Real-Numbers under Round-to-Nearest. IEEE Trans. Computers 65 (7) (2016)
Javier Hormigo, Julio Villalba
Simplified floating-point units for high dynamic range image and video systems. ISCE (2015)
Sergio D. Muñoz, Javier Hormigo
Improving fixed-point implementation of QR decomposition by rounding-to-nearest. ISCE (2015)
Sergio D. Muñoz, Javier Hormigo
High-Throughput FPGA Implementation of QR Decomposition. IEEE Trans. Circuits Syst. II Express Briefs (9) (2015)
Javier Hormigo, Julio Villalba
Optimizing DSP circuits by a new family of arithmetic operators. ACSSC (2014)
Javier Hormigo, Gabriel Caffarena, Juan P. Oliver, Eduardo I. Boemo
Self-Reconfigurable Constant Multiplier for FPGA. ACM Trans. Reconfigurable Technol. Syst. 6 (3) (2013)
Julio Villalba, Javier Hormigo, Francisco Corbera, Mario A. González, Emilio L. Zapata
Efficient floating-point representation for balanced codes for FPGA devices. ICCD (2013)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
Multioperand Redundant Adders on FPGAs. IEEE Trans. Computers 62 (10) (2013)
Sonia González-Navarro, Javier Hormigo, Michael J. Schulte
A study of decimal left shifters for binary numbers. Inf. Comput. 216 (2012)
Julio Villalba, Tomás Lang, Javier Hormigo
Radix-2 Multioperand and Multiformat Streaming Online Addition. IEEE Trans. Computers 61 (6) (2012)
Carlos Diego Moreno-Moreno, Pilar Martínez, Francisco Bellido, Javier Hormigo, Manuel Ortiz, Francisco J. Quiles
Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. IT Revolutions (2011)
Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
High-Speed Algorithms and Architectures for Range Reduction Computation. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Francisco J. Jaime, Miguel A. Sanchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
Enhanced Scaling-Free CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael J. Schulte, John Glossner
CORDIC-based LMMSE equalizer for Software Defined Radio. ICSAMOS (2010)
Francisco J. Quiles, Manuel Ortiz, María Brox, Carlos Diego Moreno-Moreno, Javier Hormigo, Julio Villalba
UCORE: Reconfigurable Platform for Educational Purposes. ReConFig (2010)
Carlos Diego Moreno-Moreno, Francisco J. Quiles, Manuel Ortiz, María Brox, Javier Hormigo, Julio Villalba, Emilio L. Zapata
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. ICECS (2009)
Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata
Efficient Implementation of Carry-Save Adders in FPGAs. ASAP (2009)
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
Pipelined Architecture for Additive Range Reduction. J. Signal Process. Syst. 53 (1-2) (2008)
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
SIMD Enhancements for a Hough Transform Implementation. DSD (2008)
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
New SIMD instructions set for image processing applications enhancement. ICIP (2008)
Julio Villalba, Javier Hormigo, Tomás Lang
Improving the Throughput of On-line Addition for Data Streams. ASAP (2007)
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
Pipelined Range Reduction for Floating Point Numbers. ASAP (2006)
Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata
SAD computation based on online arithmetic for motion estimation. Microprocess. Microsystems 30 (5) (2006)
Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata
Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL (2006)
Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata
On-line Multioperand Addition Based on On-line Full Adders. ASAP (2005)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
CORDIC Processor for Variable-Precision Interval Arithmetic. J. VLSI Signal Process. 37 (1) (2004)
Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata
Evaluation of Elementary Functions Using Multimedia Features. IPDPS (2004)
Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides
Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL (2004)
Gabriel Cristóbal, Sylvain Fischer, Manuel Forero-Vargas, Rafael Redondo, Javier Hormigo
Texture segmentation and analysis using local spectral methods. ISSPA (1) (2003)
Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata
Polynomial Evaluation on Multimedia Processors. ASAP (2002)
Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata
MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) (2000)
Javier Hormigo, Julio Villalba, Michael J. Schulte
A Hardware Algorithm for Variable-Precision Logarithm. ASAP (2000)
Gabriel Cristóbal, Javier Hormigo
Texture segmentation through eigen-analysis of the Pseudo-Wigner distribution. Pattern Recognit. Lett. 20 (3) (1999)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO (1999)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic (1999)
Javier Hormigo, Gabriel Cristóbal
High resolution spectral analysis of images using the pseudo-Wigner distribution. IEEE Trans. Signal Process. 46 (6) (1998)
Javier Hormigo, Julio Villalba, Emilio L. Zapata
A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. SCAN (1998)