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Efficient Implementation of Carry-Save Adders in FPGAs.
Javier Hormigo
Manuel Ortiz
Francisco J. Quiles
Francisco J. Jaime
Julio Villalba
Emilio L. Zapata
Published in:
ASAP (2009)
Keyphrases
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efficient implementation
hardware implementation
field programmable gate array
programmable logic
parallel architectures
active set
efficient processing
hardware software
image processing algorithms
highly parallel
embedded systems
hardware design
low cost
multiple valued
fpga technology
bit parallel