Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources.
Gabriel CaffarenaJuan A. LópezCarlos CarrerasOctavio Nieto-TaladrizPublished in: SoC (2006)
Keyphrases
- real time image processing
- signal processing
- digital signal processing
- high speed
- verilog hdl
- systolic array
- embedded systems
- resource allocation
- real time
- field programmable gate array
- hardware implementation
- digital signal
- knowledge representation
- low cost
- resource management
- digital signal processor
- parallel implementation
- fpga implementation
- smart camera
- combining multiple
- web resources
- computer vision