Susana Patón

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 18

Top Topics

Matlab Simulink

Tensor Factorization

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Nordin Zbida, Susana Patón, Eric Gutierrez
-order Noise Shaped Multistage Open-Loop Current Controlled Oscillator-based ADC with Non-Linearity Compensation. ISCAS (2024)
Victor Medina, Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Luis Hernández, Susana Patón
Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal. IEEE Trans. Circuits Syst. II Express Briefs 71 (6) (2024)
Victor Medina, Rubén Garvi, Eric Gutierrez, Susana Patón, Luis Hernández
A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón
Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. DCIS (2023)
Pablo Vera, Dietmar Straeussnigg, Victor Medina, Luis Hernández, Susana Patón
Optimal reconfiguration instant in ΣΔ Modulators. ISCAS (2022)
Pablo Vera, Andreas Wiesbauer, Susana Patón
An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals. Sensors 22 (19) (2022)
Eric Gutierrez, Carlos Perez, Susana Patón, Luis Hernández
Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs. MWSCAS (2020)
Pablo Vera, Susana Patón
DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer. DCIS (2020)
Victor Medina, Susana Patón, Eric Gutierrez, Luis Hernández
A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding. ISCAS (2020)
Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. ISCAS (2020)
Victor Medina, Leidy Mabel Alvero-Gonzalez, Eric Gutierrez, Susana Patón, Luis Hernández
Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros. ICECS (2019)
Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Pablo Vera, Susana Patón, Dietmar Straeussnigg
Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators. ISCAS (2019)
Luis Hernández, Enrique Prefasi, Susana Patón, Eric Gutierrez
VCO-ADC Resolution Enhancement Using Maximum Length Sequences. ISCAS (2018)
Eric Gutierrez, Luis Hernández, Susana Patón, Pieter Rombouts
Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. ICECS (2018)
Andrés Quintero, Carlos Perez, Eric Gutierrez, Luis Hernández, Susana Patón
Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array. MWSCAS (2017)
Laura Conesa-Peraleja, Susana Patón, Dietmar Straeussnigg, Andreas Wiesbauer
Signal boosting to extend the bandwidth of oversampled converters. ICECS (2016)
Juan A. Torreño, Susana Patón, Laura Conesa-Peraleja, Luis Hernández, Dietmar Straeussnigg
A noise coupled ΣΔ architecture using a Non Uniform Quantizer. NORCAS (2015)
Enrique Prefasi, Eric Gutierrez, Luis Hernández, Susana Patón, Sergio Walter, Ulrich Gaier
, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO. ICECS (2014)
Laura Conesa-Peraleja, Susana Patón
Time difference amplifiers to improve the dynamic range of MASH time encoded ADCs. MWSCAS (2014)
Luis Hernández, Enrique Prefasi, Susana Patón
A distortion corrected passive RC noise shaping ADC for biomedical applications. ISCAS (2013)
Juan A. Torreño, Susana Patón, Luis Hernández, Enrique Prefasi, M. Presicce, G. Paoli
A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator. ISCAS (2013)
Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts
Analysis of VCO based noise shaping ADCs linearized by PWM modulation. ICECS (2012)
Enrique Prefasi, Susana Patón, Luis Hernández
65 nm CMOS Circuit. IEEE J. Solid State Circuits 46 (7) (2011)
Enrique Prefasi, Susana Patón, Luis Hernández, Richard Gaggl, Andreas Wiesbauer, Joerg Hauptmann
A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. ESSCIRC (2010)
Susana Patón, Juan A. Torreño, Enrique Prefasi, Luis Hernández
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters. ISCAS (2010)
Luis Hernández, Jorge Fernandez, Enrique Prefasi, Susana Patón
A time encoded decimation filter for noise shaped power DACs. ISCAS (2010)
Luis Hernández, Enrique Prefasi, Ernesto Pun, Susana Patón
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. IEEE Trans. Circuits Syst. II Express Briefs (1) (2009)
Enrique Prefasi, Ernesto Pun, Luis Hernández, Susana Patón
Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer. ICECS (2009)
Enrique Prefasi, Luis Hernández, Susana Patón, Andreas Wiesbauer, Richard Gaggl, Ernesto Pun
, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS. IEEE J. Solid State Circuits 44 (10) (2009)
Luis Hernández, Susana Patón, Enrique Prefasi
An A/D converter based on pulse width modulation and the walsh-hadamard transform. ICECS (2008)
Luis Hernández, Susana Patón
Resolution enhancement of sigma-delta modulators using a tracking digital filter. ICECS (2008)
Luis Hernández, Susana Patón, Andreas Wiesbauer
Spectral shaping of clock jitter errors for continuous time sigma-delta modulators. ISCAS (2006)
Susana Patón, Manuel Sanchez-Renedo, Luis Hernández, Enrique Prefasi, Andreas Wiesbauer, Antonio Di Giandomenico, David San Segundo
Design of Cascaded Continuous-Time Sigma-Delta Modulators. ICECS (2006)
Manuel Sanchez-Renedo, Susana Patón, Luis Hernández
A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. ICECS (2006)
Luis Hernández, Enrique Prefasi, Susana Patón, Pieter Rombouts
Synthesis of sigma delta modulators employing continuous time delays. ISCAS (4) (2005)
Luis Hernández, Pieter Rombouts, Enrique Prefasi, Susana Patón, Mario Garcia, Celia Lopez
A jitter insensitive continuous-time ΣΔ modulator using transmission lines. ICECS (2004)
Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits 39 (7) (2004)
Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. CICC (2004)
Luis Hernández, Andreas Wiesbauer, Susana Patón, Antonio Di Giandomenico
Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction. ISCAS (1) (2004)
Luis Hernández, Susana Patón
Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. ISCAS (1) (2003)
Antonio Di Giandomenico, Susana Patón, Andreas Wiesbauer, Luis Hernández, Thomas Pötscher, Lukas Dörrer
A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. ESSCIRC (2003)
Luis Hernández, Susana Patón
A superregenerative receiver for phase and frequency modulated carriers. ISCAS (3) (2002)
Luis Hernández, Susana Patón
A continuous-time noise-shaping modulator for logarithmic A/D conversion. ISCAS (2) (1999)