Martin Clara

Publication Activity (10 Years)

Years Active: 2002-2021
Publications (10 Years): 3

Top Topics

Radio Frequency

Received Signal Strength

Localization Algorithm

Top Venues

IEEE J. Solid State Circuits

Publications

Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. ISSCC (2021)
Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. IEEE J. Solid State Circuits 56 (12) (2021)
Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. ISSCC (2021)
Gil Engel, Martin Clara, Haiyang Zhu, Paul Wilkins
A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout. VLSIC (2015)
Daniel Gruber, Martin Clara, Berthold Seger
A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS. ESSCIRC (2012)
Martin Clara, Nicola Da Dalt
Jitter Noise of Sampled Multitone Signals. IEEE Trans. Circuits Syst. II Express Briefs (10) (2011)
Martin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl
A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS. ESSCIRC (2008)
Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS. ISSCC (2007)
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS CoRR (2007)
Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl, Martin Clara, Luis Hernández, Daniel Gruber
Clock jitter compensation for current steering DACs. ISCAS (2006)
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS. IEEE J. Solid State Circuits 40 (7) (2005)
Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits 39 (7) (2004)
Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. CICC (2004)
Dario Giotta, Peter Pessl, Martin Clara, Wolfgang Klatzer, Richard Gaggl
Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS. ESSCIRC (2004)
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS. ESSCIRC (2004)
Martin Clara, Andreas Wiesbauer, Wolfgang Klatzer
Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors. ISCAS (1) (2004)
Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS. DATE (2004)
Martin Clara, Andreas Wiesbauer, Franz Kuttner
A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS. CICC (2002)
Andreas Wiesbauer, Martin Clara, Moritz Harteneck, Thomas Pötscher, Berthold Seger, Christoph Sandner, Christian Fleischhacker
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. IEEE J. Solid State Circuits 37 (7) (2002)