Kamran Azadet

Publication Activity (10 Years)

Years Active: 1994-2021
Publications (10 Years): 4

Top Topics

Received Signal Strength

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. ISSCC (2021)
Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. ISSCC (2021)
Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. IEEE J. Solid State Circuits 56 (12) (2021)
Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. ISSCC (2021)
Rui Wang, Yang You, Guoying Wu, Xiaoke Wen, Tianshi He, Jinghong Chen, Kamran Azadet, Ping Gui
A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration. MWSCAS (2015)
Taesong Hwang, Kamran Azadet, Ross S. Wilson, Jenshan Lin
Nonlinearity Modeling of a Chireix Outphasing Power Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Rui Wang, Xiaoke Wen, Kamran Azadet, Changzhi Li, Jinghong Chen
A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS. ISCAS (2012)
Meng Yu, Jing (Tiffany) Li, Rick S. Blum, Kamran Azadet
Toward Maximizing Throughput in Wireless Relay: A General User Cooperation Model. CISS (2007)
Jinghong Chen, Fadi Saibi, Eduard Säckinger, Joseph H. Othmer, Meng-Lin (Mark) Yu, Fuji Yang, Jenshan Lin, Titus Huang, Tingping Liu, Kamran Azadet
A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication. IEEE J. Solid State Circuits 41 (8) (2006)
Jinghong Chen, Fadi Saibi, Eduard Säckinger, Kamran Azadet, Joe Othmer, Mark Yu, Fuji Yang, Jenshan Lin, Titus Huang, Tingping Liu
An integrated CMOS transceiver for a 40Gb/s SCM optical communication system. CICC (2005)
G. Ding, Catherine Dehollain, Michel J. Declercq, Kamran Azadet
Frequency-interleaving technique for high-speed A/D conversion. ISCAS (1) (2003)
Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Michael Shaffer, Leilei Song, Meng-Lin Yu
Equalization and FEC techniques for optical transceivers. IEEE J. Solid State Circuits 37 (3) (2002)
Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.
A low power adaptive filter using dynamic reduced 2's-complement representation. CICC (2002)
Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.
The use of reduced two's-complement representation in low-power DSP design. ISCAS (1) (2002)
Kamran Azadet, Erich Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Mike Shaffer, Leilei Song, Meng-Lin Yu
DSP techniques for optical transceivers. CICC (2001)
Erich F. Haratsch, Kamran Azadet
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. IEEE J. Solid State Circuits 36 (3) (2001)
Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet
Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. ICC (1) (2000)
Erich F. Haratsch, Kamran Azadet
Pipelined reduced-state sequence estimation. GLOBECOM (2000)
Erich F. Haratsch, Kamran Azadet
High-speed reduced-state sequence estimation. ISCAS (2000)
Erich F. Haratsch, Kamran Azadet
A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet. CICC (2000)
Tracy C. Denk, Chris J. Nicol, Patrik Larsson, Kamran Azadet
Reconfigurable hardware for efficient implementation of programmable FIR filters. ICASSP (1998)
Kamran Azadet, Chris J. Nicole
Low-power equalizer architectures for high-speed modems. IEEE Commun. Mag. 36 (10) (1998)
Marc J. Loinaz, Kanwar Jit Singh, Andrew J. Blanksby, David A. Inglis, Kamran Azadet, Bryan D. Ackland
A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s. IEEE J. Solid State Circuits 33 (12) (1998)
Chris J. Nicol, Patrik Larsson, Kamran Azadet, Jay H. O'Neill
A low-power 128-tap digital adaptive equalizer for broadband modems. IEEE J. Solid State Circuits 32 (11) (1997)
Kamran Azadet, Alex G. Dickinson, David A. Inglis
A Mismatch-Free CMOS Dynamic Voltage Comparator. ISCAS (1995)
F. Yang, PatrickSenn Loumeaeu, Kamran Azadet, P. Senn
The Design of CMOS Transconductor for High Frequency Continuous-Time Filter Applications. ISCAS (1994)
Kamran Azadet, J. Porte, F. Yang, J. E. D. Hurwitz
Mixed-Mode Continuous-Time Video Acquisition Filters. ISCAS (1994)