Erich F. Haratsch

Publication Activity (10 Years)

Years Active: 2000-2020
Publications (10 Years): 21

Top Venues

CoRR

HPCA

ISIT

IEEE J. Sel. Areas Commun.

Technical University Munich (PHD)

Education History

Technical University Munich

PHD

Publications

Pengfei Huang, Yi Liu, Xiaojie Zhang, Paul H. Siegel, Erich F. Haratsch
Syndrome-Coupled Rate-Compatible Error-Correcting Codes: Theory and Application. IEEE Trans. Inf. Theory 66 (4) (2020)
Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu
Read Disturb Errors in MLC NAND Flash Memory. CoRR (2018)
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation. SIGMETRICS (Abstracts) (2018)
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation. CoRR (2018)
Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming. CoRR (2018)
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness. HPCA (2018)
Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Saugata Ghose, Onur Mutlu
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory. CoRR (2018)
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation. Proc. ACM Meas. Anal. Comput. Syst. 2 (3) (2018)
Anxiao Jiang, Pulakesh Upadhyaya, Erich F. Haratsch, Jehoshua Bruck
Correcting errors by natural redundancy. ITA (2017)
Pengfei Huang, Yi Liu, Xiaojie Zhang, Paul H. Siegel, Erich F. Haratsch
Syndrome-coupled rate-compatible error-correcting codes. ITW (2017)
Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. HPCA (2017)
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery. CoRR (2017)
Pengfei Huang, Yi Liu, Xiaojie Zhang, Paul H. Siegel, Erich F. Haratsch
Syndrome-Coupled Rate-Compatible Error-Correcting Codes. CoRR (2017)
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives. Proc. IEEE 105 (9) (2017)
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives. CoRR (2017)
Meysam Asadi, Erich F. Haratsch, Aleksandar Kavcic, Narayana Prasad Santhanam
Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs. IEEE J. Sel. Areas Commun. 34 (9) (2016)
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory. IEEE J. Sel. Areas Commun. 34 (9) (2016)
Yue Li, Hakim Alhussien, Erich F. Haratsch, Anxiao Andrew Jiang
A study of polar codes for MLC NAND flash memories. ICNC (2015)
Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. HPCA (2015)
Meysam Asadi, Erich F. Haratsch, Aleksandar Kavcic, Narayana P. Santhanam
Write process modeling in MLC flash memories using renewal theory. ISIT (2015)
Qing Li, Huan Chang, Anxiao Jiang, Erich F. Haratsch
Joint decoding of content-replication codes for flash memories. Allerton (2015)
Qing Li, Anxiao Jiang, Erich F. Haratsch
Noise modeling and capacity analysis for NAND flash memories. ISIT (2014)
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman S. Unsal, Adrián Cristal, Ken Mai
Neighbor-cell assisted error correction for MLC NAND flash memories. SIGMETRICS (2014)
Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. ICCD (2013)
Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. DATE (2013)
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal, Osman S. Ünsal, Ken Mai
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. ICCD (2012)
Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. DATE (2012)
Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA (2011)
Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai
FPGA-Based Solid-State Drive Prototyping Platform. FCCM (2011)
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei
Serial Sum-Product Architecture for Low-Density Parity-Check Codes. ICCCN (2007)
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. GLOBECOM (2007)
Hao Zhong, Tong Zhang, Erich F. Haratsch
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor. ISCAS (2006)
Hao Zhong, Tong Zhang, Erich F. Haratsch
VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel. CICC (2006)
Erich F. Haratsch, Z. A. Keirn
Digital signal processing in read channels. CICC (2005)
Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Michael Shaffer, Leilei Song, Meng-Lin Yu
Equalization and FEC techniques for optical transceivers. IEEE J. Solid State Circuits 37 (3) (2002)
Erich F. Haratsch, Kamran Azadet
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. IEEE J. Solid State Circuits 36 (3) (2001)
Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet
Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. ICC (1) (2000)
Erich F. Haratsch, Kamran Azadet
Pipelined reduced-state sequence estimation. GLOBECOM (2000)
Erich F. Haratsch, Kamran Azadet
High-speed reduced-state sequence estimation. ISCAS (2000)
Erich F. Haratsch, Kamran Azadet
A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet. CICC (2000)

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Publication Activity (10 Years)

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Erich F. Haratsch