A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.
Edwin ThallerRun LevingerEvgeny ShumakerAryeh FarberSergey BershanskyNir GeronAshoke RaviRotem BaninJasmin KadryGil HorovitzChristian KrassnitzerChristoph DullerPatrick TortaMark ElzingaKamran AzadetPublished in: ISSCC (2021)