A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS.

Martin Clara Andreas Wiesbauer Franz Kuttner

Published in: CICC (2002)

Keyphrases

low cost
database
data sets
post processing
power consumption
artificial neural networks
high speed
circuit design
power supply
single chip
delay insensitive
genetic algorithm
case study
medical images
preprocessing step
analog vlsi