A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS.
Christoph SandnerMartin ClaraAndreas SantnerThomas HartigFranz KuttnerPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- analog to digital converter
- low power
- mixed signal
- power consumption
- low cost
- high speed
- cmos technology
- spl times
- image sensor
- vlsi circuits
- single chip
- high power
- cmos image sensor
- vlsi architecture
- wide dynamic range
- multi channel
- logic circuits
- digital signal processing
- gate array
- low power consumption
- wireless transmission
- real time
- low voltage
- power reduction
- power dissipation
- random access