Nicola Da Dalt

Publication Activity (10 Years)

Years Active: 2002-2015
Publications (10 Years): 0

Top Topics

Subspace Clustering

Communication Infrastructure

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Int. J. Circuit Theory Appl.

Publications

Ken Chang, Frank O'Mahony, Elad Alon, Hyeon-Min Bae, Nicola Da Dalt, Eric Fluhr
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. ISSCC (2015)
Dmytro Cherniak, Michael Aichner, Roberto Nonis, Nicola Da Dalt
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. ESSCIRC (2015)
Federico Cernoia, Davide Ponton, Pierpaolo Palestri, Peter Thurner, Nicola Da Dalt, Giulio Cecco, Luca Selmi
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique. Int. J. Circuit Theory Appl. 43 (6) (2015)
Nicola Da Dalt
An Analysis of Phase Noise in Realigned VCOs. IEEE Trans. Circuits Syst. II Express Briefs (3) (2014)
Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon
F6: Energy-efficient I/O design for next-generation systems. ISSCC (2014)
Nicola Da Dalt, Ajith Amerasekera
ES3: High-speed communications on 4 wheels: What's in your next car? ISSCC (2013)
Nicola Da Dalt, Peter Pridnig, Werner Grollitsch
An all-digital PLL using random modulation for SSC generation in 65nm CMOS. ISSCC (2013)
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. ISSCC (2013)
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. IEEE J. Solid State Circuits 48 (12) (2013)
Martin Clara, Nicola Da Dalt
Jitter Noise of Sampled Multitone Signals. IEEE Trans. Circuits Syst. II Express Briefs (10) (2011)
Werner Grollitsch, Roberto Nonis, Nicola Da Dalt
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. ISSCC (2010)
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. IEEE J. Solid State Circuits 45 (7) (2010)
Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. ESSCIRC (2010)
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. ESSCIRC (2009)
Stefan Mendel, Christian Vogel, Nicola Da Dalt
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming. IEEE Trans. Circuits Syst. II Express Briefs (11) (2009)
Nicola Da Dalt
Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2008)
Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2008)
Nicola Da Dalt, Claus Kropf, Markus Burian, Thomas Hartig, Hermann Eul
A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS. ISSCC (2006)
Nicola Da Dalt
Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs (11) (2006)
Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. IEEE J. Solid State Circuits 40 (7) (2005)
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. IEEE J. Solid State Circuits 40 (6) (2005)
Nicola Da Dalt
A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2005)
Nicola Da Dalt
Effect of jitter on asynchronous sampling with finite number of samples. IEEE Trans. Circuits Syst. II Express Briefs (12) (2004)
Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi
A low jitter triple-band digital LC PLL in 130nm CMOS. ESSCIRC (2004)
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture. ISCAS (4) (2004)
Nicola Da Dalt, Christoph Sandner
A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. IEEE J. Solid State Circuits 38 (7) (2003)
Nicola Da Dalt, Sven Derksen, Patrizia Greco, Christoph Sandner, Harald Schmid, Klaus Strohmayer
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology. IEEE J. Solid State Circuits 37 (7) (2002)