An all-digital PLL using random modulation for SSC generation in 65nm CMOS.

Nicola Da Dalt Peter Pridnig Werner Grollitsch

Published in: ISSCC (2013)

Keyphrases

metal oxide semiconductor
circuit design
cmos technology
low cost
cmos image sensor
power consumption
low power
nm technology
mixed signal
silicon on insulator
subspace clustering
generation process
high speed
digital curves
clustering method
computer simulation
data sets