Werner Grollitsch

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 10

Top Topics

Metal Oxide Semiconductor

Person Detection

High Speed Camera

False Detections

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Alessio Cortiula, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Luigi Grimaldi, Dmytro Cherniak, Werner Grollitsch, Roberto Nonis
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems. ISCAS (2020)
Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. IEEE Trans. Circuits Syst. II Express Briefs (8) (2020)
Dylan D'Ampolo, Andrea Bandiziol, Davide Menin, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. APCCAS (2019)
A. Cortiula, Martino Dazzi, M. Marcon, Davide Menin, M. Scapol, Andrea Bandiziol, A. Cristofoli, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. MIPRO (2019)
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. ISCAS (2018)
Andrea Bandiziol, Werner Grollitsch, Giovanni Steffan, Roberto Nonis, Pierpaolo Palestri
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Werner Grollitsch, Roberto Nonis
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS. ESSCIRC (2016)
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
Design of a transmitter for high-speed serial interfaces in automotive micro-controller. MIPRO (2016)
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. APCCAS (2016)
Andrea Cossettini, A. Cristofoli, Werner Grollitsch, L. Alves, Roberto Nonis, L. Della Ricca, Pierpaolo Palestri, Luca Selmi
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall. RTSI (2015)
Nicola Da Dalt, Peter Pridnig, Werner Grollitsch
An all-digital PLL using random modulation for SSC generation in 65nm CMOS. ISSCC (2013)
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. ISSCC (2013)
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. IEEE J. Solid State Circuits 48 (12) (2013)
Werner Grollitsch, Roberto Nonis, Nicola Da Dalt
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. ISSCC (2010)