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digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture.
Roberto Nonis
Werner Grollitsch
Thomas Santa
Dmytro Cherniak
Nicola Da Dalt
Published in:
IEEE J. Solid State Circuits (2013)
Keyphrases
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low complexity
vlsi architecture
computational complexity
motion estimation
video encoding
wireless video
bit plane
lower complexity
real time
distributed video coding
digital video
video streaming
multiple description coding
packet loss
high data rate
power consumption
mimo systems