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A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS.
Werner Grollitsch
Roberto Nonis
Nicola Da Dalt
Published in:
ISSCC (2010)
Keyphrases
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metal oxide semiconductor
circuit design
low cost
cmos technology
cmos image sensor
power consumption
silicon on insulator
mixed signal
low power
power supply
digital media
analog vlsi
vlsi circuits
fractional order
differential equations
image processing
nm technology
analog to digital converter
real time