Andrea Bevilacqua

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 49

Top Topics

Clock Frequency

Cmos Technology

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Nicolò Zugno, Andrea Bevilacqua
Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology. PRIME (2024)
Davide Pecile, Stefan Kokorovic, Alberto Gambarucci, Andrea Bevilacqua
On the Efficiency of Output-Matched Radiofrequency Power Amplifiers. PRIME (2024)
Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs. IEEE J. Solid State Circuits 59 (1) (2024)
Luca Bellemo, Andrea Bevilacqua
On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Mattia de'Michieli Vitturi, Andrea Bevilacqua, Alessandro Tadini, Augusto Neri
ELICIPY 1.0: A Python online tool for expert elicitation. SoftwareX 25 (2024)
NicolÒ Zugno, Francesco Brandonisio, Thomas Niederfriniger, Andrea Bevilacqua
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies. PRIME (2023)
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58 (3) (2023)
Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Lorenzo Tomasin, Andrea Bevilacqua
A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem. PRIME (2023)
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Lesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC (2022)
Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise. IEEE J. Solid State Circuits 57 (9) (2022)
Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications. IEEE J. Solid State Circuits 57 (7) (2022)
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC (2022)
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57 (12) (2022)
Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. ESSCIRC (2022)
Andrea Bevilacqua, Salvatore Levantino, Hua Wang
Session 20 Overview: High-Performance VCOs Rf Subcommittee. ISSCC (2021)
D. Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS. ESSCIRC (2021)
Andrea Bevilacqua, Andrea Mazzanti
Doubly-Tuned Transformer Networks: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Gianluca Marin, Kyrylo Cherniak, Volha Subotskaya, Emanuele Bodano, Christoph Sandner, Andrea Bevilacqua
Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters. ISCAS (2020)
Simone Veni, Pietro Andreani, Michele Caruso, Marc Tiebout, Andrea Bevilacqua
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO. IEEE J. Solid State Circuits 55 (9) (2020)
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects. IEEE J. Solid State Circuits 55 (7) (2020)
Matteo Bassi, Giovanni Boi, Fabio Padovan, Jonas Fritzin, Stefano Di Martino, Daniel Knauder, Andrea Bevilacqua
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS. ESSCIRC (2019)
Simone Veni, Michele Caruso, Marc Tiebout, Andrea Bevilacqua
A 17 GHz All-npn Push-Pull Class-C VCO. BCICTS (2019)
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. ESSCIRC (2019)
Gianluca Marin, Kyrylo Cherniak, Volha Subotskaya, Emanuele Bodano, Christoph Sandner, Andrea Bevilacqua
Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters. ICECS (2019)
Andrea Bilato, Vadim Issakov, Andrea Bevilacqua
A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS. BCICTS (2019)
Alberto Gatti, Giorgio Spiazzi, Andrea Gerosa, Andrea Neviani, Andrea Bevilacqua
A 130-nm CMOS Dual Input-Polarity DC-DC Converter for Low-Power Applications. ESSCIRC (2019)
Andrea Gerosa, Andrea Bevilacqua, Giorgio Spiazzi
A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology. ISCAS (2019)
Federico Pepe, Andrea Bevilacqua, Pietro Andreani
On the Remarkable Performance of the Series-Resonance CMOS Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Abani K. Patra, Andrea Bevilacqua, Ali Akhavan-Safaei
Analyzing Complex Models Using Data and Statistics. ICCS (2) (2018)
Paolo Scaramuzza, Carlo Rubino, Michele Caruso, Marc Tiebout, Andrea Bevilacqua, Andrea Neviani
Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Andrea Bevilacqua, Shidhartha Das, Pieter Harpe
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 53 (7) (2018)
Antonio Passamani, Davide Ponton, Andreas Wolter, Gerhard Knoblinger, Andrea Bevilacqua
Area w/ 2D Digital-Pre-Distortion and Package Combiner. ICECS (2018)
Hyunchol Shin, Andrea Bevilacqua, Piet Wambacq
Session 23 overview: LO generation: RF subcommittee. ISSCC (2018)
Fabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations. ISSCC (2018)
Andrea Mazzanti, Andrea Bevilacqua
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Fabio Boscolo, Fabio Padovan, Fabio Quadrelli, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset. ESSCIRC (2017)
Paolo Scaramuzza, Carlo Rubino, Marc Tiebout, Michele Caruso, M. Ortner, Andrea Neviani, Andrea Bevilacqua
Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems. ESSCIRC (2017)
Antonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani, Andrea Bevilacqua
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE. ISSCC (2017)
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers. ESSCIRC (2016)
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation. IEEE J. Solid State Circuits 51 (7) (2016)
Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (6) (2016)
Andrea Mazzanti, Andrea Bevilacqua
On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2015)
Matteo Bassi, Junlei Zhao, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto
and 16% PAE in 28 nm CMOS LP. IEEE J. Solid State Circuits 50 (7) (2015)
Antonio Passamani, Davide Ponton, Gerhard Knoblinger, Andrea Bevilacqua
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs. NORCAS (2015)
Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation. ESSCIRC (2015)
Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Andrea Bevilacqua, Andrea Neviani
Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications. ICECS (2014)
Fabio Padovan, Andrea Bevilacqua, Andrea Neviani
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS. ESSCIRC (2014)
Junlei Zhao, Matteo Bassi, Andrea Bevilacqua, Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto
A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP. ESSCIRC (2014)
Matteo Bassi, Michele Caruso, Andrea Bevilacqua, Andrea Neviani
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer. IEEE J. Solid State Circuits 48 (7) (2013)
Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani
A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS. ISSCC (2013)
Michele Caruso, Matteo Bassi, Andrea Bevilacqua, Andrea Neviani
Wideband 2-16GHz local oscillator generation for short-range radar applications. ESSCIRC (2013)
Andrea Bevilacqua, Pietro Andreani
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator. IEEE Trans. Circuits Syst. II Express Briefs (1) (2012)
Matteo Bassi, Michele Caruso, Andrea Bevilacqua, Andrea Neviani
A 1.75-15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS. ESSCIRC (2012)
Andrea Neviani, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig
Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications. ICICDT (2012)
Andrea Bevilacqua, Pietro Andreani
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2012)
Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2012)
Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani
A SiGe bipolar VCO for backhaul E-band communication systems. ESSCIRC (2012)
Andrea Bevilacqua, Pietro Andreani
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory. ISCAS (2011)
Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS. IEEE J. Solid State Circuits 46 (7) (2011)
Andrea Bevilacqua, Pietro Andreani
A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2. NORCHIP (2011)
Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints. ISCAS (2011)
Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request. ESSCIRC (2010)
Silvia Soldà, Michele Caruso, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
Low-power UWB transmitter using a combined mixer and power amplifier. ISCAS (2010)
Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani
A digitally programmable ring oscillator in the UWB range. ISCAS (2010)
Matteo Camponeschi, Andrea Bevilacqua, Andrea Neviani, Pietro Andreani
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end. ISCAS (2010)
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. IEEE J. Solid State Circuits 45 (7) (2010)
Stefano Dal Toso, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks. ISCAS (2010)
Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. ESSCIRC (2010)
Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems. IEEE J. Solid State Circuits 44 (2) (2009)
Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani
An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2009)
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. ESSCIRC (2009)
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. ISSCC (2008)
Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits 43 (12) (2008)
Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. IEEE J. Solid State Circuits 43 (12) (2008)
Andrea Gerosa, Maurizio Dalla Costa, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani
An energy-detector for non-coherent impulse-radio UWB receivers. ISCAS (2008)
Silvia Soldà, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
Analog decoding of trellis coded modulation for multi-level flash memories. ISCAS (2008)
Andrea Bevilacqua, Matteo Camponeschi, Marc Tiebout, Andrea Gerosa, Andrea Neviani
Design of broadband inductorless LNAs in ultra-scaled CMOS technologies. ISCAS (2008)
Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani
An Integrated Solution for Suppressing WLAN Signals in UWB Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2007)
Andrea Bevilacqua, Alessio Vallese, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers. ISSCC (2007)
Andrea Bevilacqua, Federico P. Pavan, Christoph Sandner, Andrea Gerosa, Andrea Neviani
Transformer-Based Dual-Mode Voltage-Controlled Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (4) (2007)
Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS. ESSCIRC (2007)
Andrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani
Quadrature VCOs Based on Coupled PLLs. ISCAS (2007)
Andrea Maniero, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency. ICECS (2006)
Andrea Gerosa, Andrea Xotta, Andrea Bevilacqua, Andrea Neviani
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2006)
Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani
A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection. ICECS (2006)
Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter. ISCAS (2006)
Andrea Bevilacqua, Francesco Svelto
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers. IEEE Trans. Circuits Syst. II Express Briefs (3) (2005)
Andrea Bevilacqua, Ali M. Niknejad
An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers. IEEE J. Solid State Circuits 39 (12) (2004)