Andrea L. Lacaita

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 40

Top Topics

Wireless Transmission

Metal Oxide Semiconductor

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58 (3) (2023)
Giacomo Castoro, Simone Mattia Dartizio, Andrea L. Lacaita, Salvatore Levantino
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Francesco Tesolin, Simone Mattia Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits 58 (9) (2023)
Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. ISSCC (2023)
Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ISSCC (2023)
Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. IEEE J. Solid State Circuits 58 (12) (2023)
Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, Luca Bertulessi, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits (2023)
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Lesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC (2022)
Simone Mattia Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57 (6) (2022)
Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57 (2) (2022)
Luca Bertulessi, Dmytro Cherniak, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (5) (2022)
Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Lorenzo Scaletti, Mario Mercandelli, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57 (12) (2022)
Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. IEEE J. Solid State Circuits 57 (6) (2022)
Angelo Parisi, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity. ICECS (2021)
Francesco Buccoleri, Andrea Bonfanti, Andrea L. Lacaita
A Generalization of the Groszkowski's Result in Differential Oscillator Topologies. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC (2021)
Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55 (12) (2020)
Aurelio Mannara, Alessandro S. Spinelli, Andrea L. Lacaita, Christian Monzio Compagnoni
Current Transport in Polysilicon-channel GAA MOSFETs: A Modeling Perspective. ESSDERC (2019)
Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2019)
Luigi Grimaldi, Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. ISSCC (2019)
Alessio Santiccioli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC (2019)
Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits 54 (12) (2019)
Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits 54 (11) (2019)
Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. ISCAS (2018)
Mauro Leoncini, Andrea Bonfanti, Salvatore Levantino, Andrea L. Lacaita
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Mario Mercandelli, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits 53 (11) (2018)
Alessandro Truppi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino, Marco Ronchi, Marco Sosio
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. ISCAS (2018)
Alessandro S. Spinelli, Christian Monzio Compagnoni, Andrea L. Lacaita
Random Dopant Fluctuation and Random Telegraph Noise in Nanowire and Macaroni MOSFETs. ESSDERC (2018)
Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. ICECS (2018)
Alessandro S. Spinelli, Christian Monzio Compagnoni, Andrea L. Lacaita
Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices. Comput. 6 (2) (2017)
Christian Monzio Compagnoni, Akira Goda, Alessandro S. Spinelli, Peter Feeley, Andrea L. Lacaita, Angelo Visconti
Reviewing the Evolution of the NAND Flash Technology. Proc. IEEE 105 (9) (2017)
Tuan Minh Vo, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. ISCAS (2017)
Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
An efficient tool for the assisted design of SAR ADCs capacitive DACs. Integr. 53 (2016)
Nicola Ciocchini, Mario Laudato, Andrea L. Lacaita, Daniele Ielmini, M. Boniardi, E. Varesi, Paolo Fantini
Bipolar-switching operated phase change memory (PCM) for improved high-temperature reliability. ESSDERC (2016)
Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (6) (2016)
Stefano Brenna, Luca Bettini, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters. NORCAS (2015)
Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
A tool for the assisted design of charge redistribution SAR ADCs. DATE (2015)
Salvatore Levantino, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori, Andrea L. Lacaita
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. IEEE J. Solid State Circuits 50 (11) (2015)
Stefano Brenna, Andrea Bonfanti, Andrea Abba, Francesco Caponio, Andrea L. Lacaita
Analysis and optimization of a SAR ADC with attenuation capacitor. MIPRO (2014)
Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita
A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs. MIPRO (2014)
Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. ISSCC (2014)
Giovanni M. Paolucci, M. Bertuccio, C. Monzio Compagnoni, Silvia Beltrami, Alessandro S. Spinelli, Andrea L. Lacaita, Angelo Visconti
Cycling-induced threshold-voltage instabilities in nanoscale NAND flash memories: Sensitivity to the array background pattern. ESSDERC (2014)
Halid Mulaosmanovic, C. Monzio Compagnoni, N. Castellani, G. Carnevale, D. Ventrice, Paolo Fantini, Alessandro S. Spinelli, Andrea L. Lacaita, A. Benvenuti
Data regeneration and disturb immunity of T-RAM cells. ESSDERC (2014)
Stefano Brenna, Andrea Bonetti, Andrea L. Lacaita, Andrea Bonfanti
A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs. UKSim (2014)
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2.9 A Background calibration technique to control bandwidth in digital PLLs. ISSCC (2014)
Salvatore Levantino, Giovanni Marzin, Carlo Samori, Andrea L. Lacaita
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. IEEE J. Solid State Circuits 48 (10) (2013)
Marcello Calabrese, Carmine Miccoli, Christian Monzio Compagnoni, Luca Chiavarone, Silvia Beltrami, Andrea Parisi, Sebastiano Bartolone, Andrea L. Lacaita, Alessandro S. Spinelli, Angelo Visconti
Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology. ICICDT (2013)
Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori, Andrea L. Lacaita
Simulating phase noise induced from cyclostationary noise sources. ISCAS (2013)
Giovanni Marzin, Andrea Fenaroli, Giovanni Marucci, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A spur cancellation technique for MDLL-based frequency synthesizers. ISCAS (2013)
Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. IEEE J. Solid State Circuits 48 (10) (2013)
Andrea Fenaroli, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Background adaptive linearization of high-speed digital-to-analog Converters. ISCAS (2013)
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. ISSCC (2012)
Federico Pepe, Andrea Bonfanti, Andrea L. Lacaita
A fast and accurate simulation method of impulse sensitivity function in oscillators. MIPRO (2012)
Andrea Bonfanti, Federico Pepe, Carlo Samori, Andrea L. Lacaita
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2012)
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. IEEE J. Solid State Circuits 47 (12) (2012)
Salvatore Levantino, Paolo Maffezzoni, Federico Pepe, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita
Efficient Calculation of the Impulse Sensitivity Function in Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (10) (2012)
Paolo Maffezzoni, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, Dario D'Amore, Mauro Santomauro
Behavioral phase-noise analysis of charge-pump phase-locked loops. ECCTD (2011)
Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. IEEE J. Solid State Circuits 46 (3) (2011)
Carlo Samori, Marco Zanuso, Salvatore Levantino, Andrea L. Lacaita
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. ISCAS (2011)
Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC (2011)
Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Integrated Jitter at 4.5-mW Power. IEEE J. Solid State Circuits 46 (12) (2011)
Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. ISSCC (2010)
Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010)
Andrea Bonfanti, M. Ceravolo, Guido Zambra, Riccardo Gusmeroli, Tommaso Borghi, Alessandro S. Spinelli, Andrea L. Lacaita
A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission. ESSCIRC (2010)
Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Carlo Samori, Andrea L. Lacaita
Time-to-digital converter with 3-ps resolution and digital linearization algorithm. ESSCIRC (2010)
Salvatore Levantino, Luca Collamati, Carlo Samori, Andrea L. Lacaita
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)
Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2010)
Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ISSCC (2010)
Marco Zanuso, Davide Tasca, Salvatore Levantino, Andrea Donadel, Carlo Samori, Andrea L. Lacaita
Noise Analysis and Minimization in Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs (11) (2009)
Salvatore Levantino, Marco Zanuso, Davide Tasca, Carlo Samori, Andrea L. Lacaita
An all-digital architecture for low-jitter regulated delay lines. ICECS (2009)
Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita
A glitch-corrector circuit for low-spur ADPLLs. ICECS (2009)
Luigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter. IEEE J. Solid State Circuits 43 (5) (2008)
Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Quantization Effects in All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs (12) (2007)
Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita
A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN. ESSCIRC (2007)
Tommaso Borghi, Andrea Bonfanti, Guido Zambra, Riccardo Gusmeroli, Andrea L. Lacaita, Alessandro S. Spinelli, Gytis Baranauskas
An integrated low-noise multichannel system for neural signals amplification. ESSCIRC (2007)
Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Multiphase LC oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2006)
Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2006)
Luca Romanò, Luigi Panseri, Carlo Samori, Andrea L. Lacaita
Matching requirements in LINC transmitters for OFDM signals. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2006)
Luigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. CICC (2006)
Luca Romanò, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS. IEEE J. Solid State Circuits 41 (11) (2006)
Salvatore Levantino, Andrea Bonfanti, Luca Romanò, Carlo Samori, Andrea L. Lacaita
Differential tuning oscillators with reduced flicker noise upconversion. ICECS (2004)
Salvatore Levantino, Luca Romanò, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita
Phase noise in digital frequency dividers. IEEE J. Solid State Circuits 39 (5) (2004)
Luca Romanò, Salvatore Levantino, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita
Phase noise and accuracy in quadrature oscillators. ISCAS (1) (2004)
S. Pellerano, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. IEEE J. Solid State Circuits 39 (2) (2004)
Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita
Fast-switching analog PLL with finite-impulse response. ISCAS (4) (2004)
Salvatore Levantino, Marco Milani, Carlo Samori, Andrea L. Lacaita
Fast-switching analog PLL with finite-impulse response. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2004)
Luca Romanò, Carlo Samori, Salvatore Levantino, Andrea Bonfanti, Andrea L. Lacaita
A multi-tank LC-oscillator [microwave oscillator example]. ICECS (2004)
Andrea Giovanni Bonfanti, Salvatore Levantino, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita, Felice Torrisi
A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. ESSCIRC (2003)
Andrea Bonfanti, F. Amorosa, Carlo Samori, Andrea L. Lacaita
A DDS-based PLL for 2.4-GHz frequency synthesis. IEEE Trans. Circuits Syst. II Express Briefs 50 (12) (2003)
Salvatore Levantino, Carlo Samori, Andrea Bonfanti, Sander L. J. Gierkink, Andrea L. Lacaita, Vito Boccuzzi
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. IEEE J. Solid State Circuits 37 (8) (2002)
Carlo Samori, Salvatore Levantino, Andrea L. Lacaita
Integrated LC oscillators for frequency synthesis in wireless applications. IEEE Commun. Mag. 40 (5) (2002)
Alfio Zanchi, Carlo Samori, Salvatore Levantino, Andrea L. Lacaita
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. IEEE J. Solid State Circuits 36 (4) (2001)
Alfio Zanchi, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO. CICC (2001)
Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, Salvatore Levantino, Giovanni Calí
Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. IEEE J. Solid State Circuits 35 (1) (2000)
Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, P. Vita
Design Issues of LC Tuned Oscillators for Integrated Transceivers. Great Lakes Symposium on VLSI (1998)