Login / Signup
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.
Marco Zanuso
Salvatore Levantino
Carlo Samori
Andrea L. Lacaita
Published in:
ISSCC (2010)
Keyphrases
</>
high speed
wavelet transform
real time
data sets
neural network
high frequency
digital objects
simulation software