Salvatore Levantino

ORCID

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 68

Top Venues

IEEE J. Solid State Circuits

ISSCC

IEEE Trans. Circuits Syst. I Regul. Pap.

CICC

Publications

Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. ISSCC (2024)
Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. CICC (2024)
Paolo Melillo, Simone Zaffin, Mauro Leoncini, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (7) (2024)
Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. ISSCC (2024)
Pietro Salvi, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. CICC (2024)
Paolo Melillo, Mauro Leoncini, Simone Zaffin, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications. ESSCIRC (2023)
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58 (3) (2023)
Giacomo Castoro, Simone Mattia Dartizio, Andrea L. Lacaita, Salvatore Levantino
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Francesco Tesolin, Simone Mattia Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits 58 (9) (2023)
Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. ISSCC (2023)
Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ISSCC (2023)
Paolo Melillo, Simone Zaffin, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions. PRIME (2023)
Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. IEEE J. Solid State Circuits 58 (12) (2023)
Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, Luca Bertulessi, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits (2023)
Mauro Leoncini, Alessandro Bertolini, Paolo Melillo, Salvatore Levantino, Massimo Ghioni
Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control. Integr. 90 (2023)
Salvatore Levantino
Frequency Synthesizers for 5G Applications. VLSI-SoC (2022)
Lorenzo Scaletti, Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Mario Mercandelli, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS (2022)
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Lesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC (2022)
Alessandro Dago, Mauro Leoncini, Alberto Cattani, Salvatore Levantino, Massimo Ghioni
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation. PRIME (2022)
Mauro Leoncini, Paolo Melillo, Alessandro Bertolini, Salvatore Levantino, Massimo Ghioni
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control. PRIME (2022)
Rabia Tugce Yazicigil, Salvatore Levantino
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 57 (7) (2022)
Simone Mattia Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57 (6) (2022)
Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57 (2) (2022)
Luca Bertulessi, Dmytro Cherniak, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (5) (2022)
Salvatore Levantino
Recent Advances in High-Performance Frequency Synthesizer Design. CICC (2022)
Paolo Melillo, Alessandro Dago, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters. PRIME (2022)
Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Lorenzo Scaletti, Mario Mercandelli, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC (2022)
Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Luca Bertulessi, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. ISCAS (2022)
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57 (12) (2022)
Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. IEEE J. Solid State Circuits 57 (6) (2022)
Mario Mercandelli, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata, Francesco Tesolin, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea Leonardo Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC (2021)
Andrea Bevilacqua, Salvatore Levantino, Hua Wang
Session 20 Overview: High-Performance VCOs Rf Subcommittee. ISSCC (2021)
Saleh Karman, Francesco Tesolin, Salvatore Levantino, Carlo Samori
A Novel Topology of Coupled Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Mario Mercandelli, Luca Bertulessi, Carlo Samori, Salvatore Levantino
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. A-SSCC (2021)
Luca Avallone, Mario Mercandelli, Alessio Santiccioli, Michael Peter Kennedy, Salvatore Levantino, Carlo Samori
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Alessandro Garghetti, Andrea Leonardo Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS. CICC (2021)
Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC (2021)
Mauro Leoncini, Alessandro Bertolini, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
An 800-mA Time-Based Boost Converter in 0.18µm BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency. ESSCIRC (2021)
Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea Leonardo Lacaita, Carlo Samori, Salvatore Levantino
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC (2020)
Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea Leonardo Lacaita, Carlo Samori, Salvatore Levantino
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC (2020)
Luca Avallone, Michael Peter Kennedy, Saleh Karman, Carlo Samori, Salvatore Levantino
Jitter Minimization in Digital PLLs with Mid-Rise TDCs. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2020)
Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55 (12) (2020)
Tommaso Rosa, Mauro Leoncini, Salvatore Levantino, Massimo Ghioni
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition. ISCAS (2020)
Dmytro Cherniak, Carlo Samori, Salvatore Levantino
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper). CICC (2019)
Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2019)
Luigi Grimaldi, Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. ISSCC (2019)
Alessio Santiccioli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC (2019)
Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits 54 (12) (2019)
Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits 54 (11) (2019)
Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. ISCAS (2018)
Dmytro Cherniak, Luigi Grimaldi, Carlo Samori, Salvatore Levantino
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. ISCAS (2018)
Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. ISSCC (2018)
Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ISSCC (2018)
Mauro Leoncini, Andrea Bonfanti, Salvatore Levantino, Andrea L. Lacaita
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Salvatore Levantino
Digital phase-locked loops. CICC (2018)
Mario Mercandelli, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits 53 (11) (2018)
Dmytro Cherniak, Carlo Samori, Roberto Nonis, Salvatore Levantino
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Paolo Maffezzoni, Zheng Zhang, Salvatore Levantino, Luca Daniel
Variation-Aware Modeling of Integrated Capacitors Based on Floating Random Walk Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Tuan Minh Vo, Carlo Samori, Salvatore Levantino
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs. ISCAS (2018)
Alessandro Truppi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino, Marco Ronchi, Marco Sosio
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. ISCAS (2018)
Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. ICECS (2018)
Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Roberto Nonis, Carlo Samori, Salvatore Levantino
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. IEEE J. Solid State Circuits 53 (12) (2018)
Dmytro Chemiak, Salvatore Levantino, Carlo Samori, Roberto Nonis
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars. ISCAS (2017)
Tuan Minh Vo, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. ISCAS (2017)
Salvatore Levantino
Introduction to the Special Section on the 2015 Radio Frequency Integrated Circuits Symposium. IEEE J. Solid State Circuits 51 (5) (2016)
Salvatore Levantino
Bang-bang digital PLLs. ESSCIRC (2016)
Salvatore Levantino, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori, Andrea L. Lacaita
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. IEEE J. Solid State Circuits 50 (11) (2015)
Salvatore Levantino, Giovanni Marzin, Carlo Samori
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs. IEEE J. Solid State Circuits 49 (8) (2014)
Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. ISSCC (2014)
Paolo Maffezzoni, Salvatore Levantino
Phase Noise of Pulse Injection-Locked Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2014)
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2.9 A Background calibration technique to control bandwidth in digital PLLs. ISSCC (2014)
Salvatore Levantino, Giovanni Marzin, Carlo Samori, Andrea L. Lacaita
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. IEEE J. Solid State Circuits 48 (10) (2013)
Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
An efficient method to compute phase-noise in injection-locked frequency dividers. ISCAS (2013)
Salvatore Levantino
Advanced digital phase-locked loops. CICC (2013)
Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
DCO noise. ISCAS (2013)
Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Salvatore Levantino, Carlo Samori
Nonlinearity cancellation in digital PLLs (Invited paper). CICC (2013)
Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori, Andrea L. Lacaita
Simulating phase noise induced from cyclostationary noise sources. ISCAS (2013)
Giovanni Marzin, Andrea Fenaroli, Giovanni Marucci, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A spur cancellation technique for MDLL-based frequency synthesizers. ISCAS (2013)
Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. IEEE J. Solid State Circuits 48 (10) (2013)
Andrea Fenaroli, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Background adaptive linearization of high-speed digital-to-analog Converters. ISCAS (2013)
Paolo Maffezzoni, Salvatore Levantino
Phase-Noise Analysis and Simulation of LC Oscillator-Based Injection-Locked Frequency Dividers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. ISSCC (2012)
Salvatore Levantino, Paolo Maffezzoni
Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (10) (2012)
Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. IEEE J. Solid State Circuits 47 (12) (2012)
Paolo Maffezzoni, Salvatore Levantino
Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Salvatore Levantino, Paolo Maffezzoni, Federico Pepe, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita
Efficient Calculation of the Impulse Sensitivity Function in Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (10) (2012)
Paolo Maffezzoni, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, Dario D'Amore, Mauro Santomauro
Behavioral phase-noise analysis of charge-pump phase-locked loops. ECCTD (2011)
Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. IEEE J. Solid State Circuits 46 (3) (2011)
Carlo Samori, Marco Zanuso, Salvatore Levantino, Andrea L. Lacaita
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. ISCAS (2011)
Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC (2011)
Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
Integrated Jitter at 4.5-mW Power. IEEE J. Solid State Circuits 46 (12) (2011)
Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. ISSCC (2010)
Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010)
Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Carlo Samori, Andrea L. Lacaita
Time-to-digital converter with 3-ps resolution and digital linearization algorithm. ESSCIRC (2010)
Salvatore Levantino, Luca Collamati, Carlo Samori, Andrea L. Lacaita
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)

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Salvatore Levantino