A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
Simone Mattia DartizioFrancesco TesolinGiacomo CastoroFrancesco BuccoleriMichele RossoniDmytro CherniakCarlo SamoriAndrea L. LacaitaSalvatore LevantinoPublished in: IEEE J. Solid State Circuits (2023)