A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
Francesco BuccoleriSimone Mattia DartizioFrancesco TesolinLuca AvalloneAlessio SanticcioliAgata IesurumGiovanni SteffanDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore LevantinoPublished in: IEEE J. Solid State Circuits (2023)