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A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.

Giacomo CastoroSimone Mattia DartizioFrancesco TesolinFrancesco BuccoleriMichele RossoniDmytro CherniakLuca BertulessiCarlo SamoriAndrea L. LacaitaSalvatore Levantino
Published in: ISSCC (2023)
Keyphrases
  • high speed
  • digital topology
  • real time
  • circuit design
  • fuzzy logic
  • digital media