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21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.
Giovanni Marucci
Andrea Fenaroli
Giovanni Marzin
Salvatore Levantino
Carlo Samori
Andrea L. Lacaita
Published in:
ISSCC (2014)
Keyphrases
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power consumption
clock frequency
clock gating
low power
end to end delay
high speed
power reduction
data sets
power dissipation
root mean square
frequency distribution
power distribution
wind turbine
packet loss
low frequency
higher order
multiresolution