A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS.
Luigi GrimaldiLuca BertulessiSaleh KarmanDmytro CherniakAlessandro GarghettiCarlo SamoriAndrea L. LacaitaSalvatore LevantinoPublished in: ISSCC (2019)
Keyphrases
- metal oxide semiconductor
- high speed
- cmos technology
- power consumption
- circuit design
- low cost
- linear programming
- low power
- cmos image sensor
- mixed signal
- random sampling
- sampling strategy
- monte carlo
- integrated circuit
- sampling algorithm
- silicon on insulator
- objective function
- digital curves
- low voltage
- linear program
- analog vlsi
- small size
- fractional order
- sample size
- np hard
- nm technology
- real time