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Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.
Davide Tasca
Marco Zanuso
Salvatore Levantino
Carlo Samori
Andrea L. Lacaita
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2011)
Keyphrases
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low power
high speed
power consumption
low cost
single chip
wireless transmission
high power
vlsi architecture
low power consumption
vlsi circuits
digital signal processing
real time
gate array
image sensor
logic circuits
general purpose
mixed signal
power reduction
frequency band
ultra low power