A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector.
Simone Mattia DartizioMichele RossoniFrancesco TesolinGiacomo CastoroCarlo SamoriAndrea L. LacaitaSalvatore LevantinoPublished in: CICC (2024)